JPH022703A - High voltage detection circuit for semiconductor memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applied to a semiconductor memory, etc., in which information is written by ion implantation, and which detects whether an input voltage is a high voltage. The present invention relates to a high voltage detection circuit.

[Conventional technology]

N constituting the high voltage detection circuit 11 of a conventional semiconductor memory
For example, as shown in FIG. 3, the drain D and gate G of the type MOS transistor Tr are connected to each other to serve as an input terminal IN, while the substrate U is grounded. The source S of the P-type Mos+- transistor Tr2 and the substrate U are connected to the source S of the N-type MOS transistor Tr1.

The drain D of the P-type MOS transistor Trz is used as an output terminal OUT, and is also connected to the drain D of the N-type MOS transistor 'l'r=. Also, P
The gate G of the transistor Tr2 (type MOS) is at the potential Vcc.
It is connected to the power source of , and also connected to the gate G of the N-type MOS transistor Tr3.

The source S and substrate U of the N-type MOS transistor Tr3 are both grounded.

In such a semiconductor memory high voltage detection circuit, N type M
The OS transistor Tr3 is always in an ON state, and becomes an N-type MOS transistor Tr when the potential Vin of the input terminal IN is not at a high potential.

, and the P-type M'OS transistor Tr2 are turned off. Therefore, the potential Vout of the output terminal OUT becomes low level.

On the other hand, when the potential Vin of the input terminal IN increases, the input terminal IN and the N-type MO3h transistor Tr.

The potential difference between the source S and the source S increases.

Here, N-type MOS l-randisk Tr1.Tr.

and the bank gate effect voltage due to the source S potential are vthN and vt, respectively.
hN'', the potential difference between the input terminal IN and the source S of the N-type MOS transistor Tr is vth, 4
+vth,' or more, the N-type MOS transistor Tr is turned on.

As the N-type MOS transistor Tr is turned on, the potential of the source S of the P-type MOS transistor Tr2 increases. Therefore, if the threshold voltage of the P-type MOS transistor Tr is V th hp, the potential of the source S of the P-type MOS transistor Tr2 is Vcc+1Vth.
, 1 or more, the P-type MOS transistor Tr also turns on, and the potential Vou of the output terminal OUT increases.
t becomes high level.

That is, the potential Vin of the input terminal IN is Vcc+VL
When hN+VthN'+1vth,l, the level of the potential Vout at the output terminal OUT is inverted, thereby detecting whether the potential ■in at the input terminal IN is a high potential.

[Problem to be solved by the invention]

However, in the conventional semiconductor memory high voltage detection circuit described above, the potential Vin of the input terminal IN for inverting the level of the potential Vout at the output terminal OUT changes in accordance with fluctuations in the power supply potential Vcc. Therefore, as shown in FIG. 4, for example, even if the potential Vin of the input terminal IN is constant, when the potential Vcc of the power supply changes, the potential V of the output terminal OUT changes.

ut had a problem in that it was not fixed at a certain level and became unstable.

[Means to solve the problem]

In order to solve the above problems, a high voltage detection circuit for a semiconductor memory according to the present invention detects whether an input voltage is a high voltage. On the other hand, the drain is used as an output terminal, the substrate is grounded, and the drain is connected to the high threshold voltage N-type MOS transistor constituting the input vanofer, and the drain is connected to the drain of the above-mentioned N-type MOS transistor, and the source and substrate are connected to each other. A P-type MOS transistor whose gate is grounded while both are connected to a power supply, and an N-type MOS transistor whose drain and gate are connected to the source of the N-type MOS transistor and whose substrate and source are grounded. It is characterized by becoming.

[For production]

With the above configuration, the potential of the input terminal for inverting the level of the potential at the output terminal can be made not to be directly affected by fluctuations in the potential of the power supply, so that a stable output can be obtained.

Furthermore, since the input impedance is increased, the influence on the circuit that outputs the input terminal of the high voltage detection circuit can be reduced.

〔Example〕

An embodiment of the present invention will be described below based on FIGS. 1 and 2.

For example, as shown in FIG. 1, the high threshold voltage N-type MOS transistor Tr constituting the high voltage detection circuit 21 of the semiconductor memory has a gate G as an input terminal IN and a drain D as an output terminal OUT. At the same time, the substrate U is grounded to form an input buffer 22. As this high threshold voltage N-type MOS transistor Tr12, one whose threshold voltage is increased by, for example, performing ion implantation in the manufacturing process is used.

The drain D of the N-type MOS transistor 'rr+z is connected to the drain D of the P-type MOS transistor Tr. The source S1 and substrate U of this P-type MOS transistor Trll are both connected to a power source of potential Vcc, while the gate G is grounded.

In addition, the sources S of the N-type MOS transistors T'', 2
are the drains D of the N-type MOS transistors Tr, ,
and gate G are connected. This N-type MOS transistor T', 3 substrate U, and source S
is grounded.

In the above configuration, the P-type MOS transistors Tr,
Since the gate G is grounded, it is always on. Further, the N-type MOS transistor 'rr+z is turned off when the potential Vin of the input terminal IN, that is, the gate G is not at a high potential, and accordingly, the N-type MO3 transistor Tr13 is also turned off.

Therefore, the potential Vout of the output terminal 0tJT becomes high level.

On the other hand, when the potential Vin of the input terminal IN increases,
The potential of the gate G of the N-type MOS transistors Tr, , becomes high.

Here, the threshold voltage of the N-type MOS transistor 'rrtz with a high threshold voltage and the back gate effect voltage due to the potential of the source S are respectively expressed as V
thrp, and Vthrp”, and N-type MOS
Let the threshold voltage of the transistor Tr, , be vthN
Then, the potential Vin of the input terminal IN is Vthrp
+Vthrp'+vth, when it is above, N type M
The OS transistors Tr and □ are turned on.

As the N-type MOS transistor Tr, . is turned on, the potential of the gate of the N-type MOS transistor Tr11 increases, so that the N-type MOS transistor Tr, , is also turned on. Therefore, the potential Vo of the output terminal OUT
ut becomes low level.

That is, the potential Vin of the input terminal IN is Vthrp+
Since the level of the potential Vout at the output terminal OUT is inverted when Vthrp'+vthN, it is detected whether the potential Vin at the input terminal IN is a high potential.

By the way, as mentioned above, the potential V at the output terminal OUT
The first and third terms in the equation representing the potential Vin of the input terminal IN for inverting the level of out are not affected by the power supply potential Vcc. Further, the second term is influenced to some extent by the power supply potential Vcc, but the P-type MOS transistor Tr.

, and N-type MOS transistors Tr, □·Tr,.

By appropriately setting the characteristics of , the dependence on the power supply potential Vcc can be easily reduced.

Therefore, for example, as shown in FIG.
Even if cc fluctuates somewhat, the potential V at the output terminal OUT
Since the potential Vin of the input terminal IN for inverting the level of out does not change much, the level of the potential Vout at the output terminal OUT can be easily stabilized.

Also, as mentioned above, high threshold voltage N-type MO
Input buffer 22 using S transistor T r +□
By configuring , the input impedance becomes high, so that the influence on the circuit that outputs to the input terminal IN of the high voltage detection circuit 21 becomes small.

The high threshold voltage N-type MOS transistor Tr,□ is not limited to one in which ions are implanted in the manufacturing process as in this embodiment, but it may be one in which the threshold voltage is increased by ion implantation in this way. When used, the inversion level can be easily set to a desired level by controlling the amount of ion implantation. Furthermore, if the semiconductor memory used in the high voltage detection circuit 21 is a semiconductor memory in which information is written by increasing the threshold voltage of a specific MOS transistor using an ion implantation mask, the above-mentioned Since the high threshold voltage N-type MOS transistor 'rr+g can be formed at the same time, there is no need to increase the number of steps.

〔Effect of the invention〕

As described above, the high voltage detection circuit for a semiconductor memory according to the present invention uses a gate as an input terminal, and A high threshold voltage N-type MOS transistor with a drain as an output terminal and a substrate grounded to form an input cover sofa;
The drain is connected to the drain of the OS transistor, and the source and substrate are both connected to a power supply, while the gate is grounded, and the drain and gate are connected to the source of the P-type MO5) transistor and the N-type MOS transistor. On the other hand, it has a structure consisting of a substrate and an N-type MOS transistor whose source is grounded.

As a result, the potential of the input terminal for inverting the level of the potential at the output terminal can be made less dependent on the potential of the power supply, so that a stable output can be obtained. Moreover, since the human power impedance becomes high, it is possible to reduce the effect on the circuit that outputs the input terminal of the high voltage detection circuit.

[Brief explanation of the drawing]

1 and 2 show an embodiment of the present invention, in which FIG. 1 is a circuit diagram showing the configuration of a high voltage detection circuit, and FIG. 2 shows the potential Vin of the input terminal and the potential of the output terminal. Vout
It is a graph showing the relationship between 3 and 4 show conventional examples.
The figure is a circuit diagram showing the configuration of a conventional high voltage detection circuit, and FIG. 4 shows the potential Vin of the input terminal in the conventional high voltage detection circuit.
3 is a graph showing the relationship between Vout and the potential Vout of the output terminal. 21 is a high voltage detection circuit, 22 is an input buffer, Tr,
is a P-type MOS transistor, Tr, , is a high threshold voltage N-type MOS transistor, and Tr13 is an N-type MOS transistor.
It is an S transistor.

Claims (1)

[Claims] 1. In a semiconductor memory high voltage detection circuit that detects whether an input voltage is a high voltage, the gate is used as an input terminal, the drain is used as an output terminal, and the substrate is grounded to connect the input buffer. The constituent high threshold voltage N-type MOS transistors and the above-mentioned N-type MOS
A P-type MOS transistor whose drain is connected to the drain of the transistor, whose source and substrate are both connected to a power supply, and whose gate is grounded, and whose drain and gate are connected to the source of the N-type MOS transistor, A high voltage detection circuit for a semiconductor memory, comprising a substrate and an N-type MOS transistor whose source is grounded.