JPH02270421A - Oversampling device - Google Patents

Abstract

PURPOSE:To attain the oversampling with the addition of a simple circuit by providing 2 sets of D/A converters and inverters and devising the circuit so that the phase of an analog data outputted from the 2nd DA converter is retarded than that of the 1st D/A converter by one data period. CONSTITUTION:The circuit consists of a 1st D/A converter receiving a digital data sent repetitively times each and receiving a signal rising for one data period as an operating signal, a 2nd D/A converter receiving a digital data and receiving an output signal of an inverter as an opening signal, and a circuit applying arithmetic means to outputs of the 1st and 2nd D/A converters. An analog data in response to the earlier data in the digital data sent twice repetitively is outputted from the 1st D/A converter for a 2-data period. Moreover, an analog data in response to a slower data in the digital data is outputted from the 2nd D/A converter for the 2-data period.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to an oversampling device for creating an oversampling signal from a digital transmission signal by linear interpolation.

(B) Prior Art In recent years, oversampling technology has begun to be used in players such as compact discs that require digital signal processing. Such oversampling technology involves, when converting a digital transmission signal into an analog signal at a predetermined sampling period, create interpolated data to be inserted between the sampling periods by numerical calculation of the data and superimpose it on the original signal. It is something.

When this oversampling technology is used, it is possible to use a low-order low-pass filter that removes noise from analog signals after DA conversion. Therefore, when used in, for example, a compact disc player, the reproduced audio It is possible to suppress high-frequency group delay distortion. Furthermore, dynamic range and 5/N can be improved. For details on such oversampling technology, please see, for example, the magazine Radio Technology, July 1988 issue (special edition), pages 104-P.
107, and we will discuss it here.

Explanation will be omitted.

As an example of the above-mentioned oversampling technique, there is one disclosed in the magazine Radio Technology July 1988 issue P141 to P143. This is created by linear interpolation (average value interpolation) of interpolated data around 1. Specifically, as shown in Figure 7, two DA converters (DACI
, DAC2) (30) (31) and an operational amplifier (32) that arithmetic averages the outputs, and a data flow of 18Ts.
Ts delay circuit (33) is used to delay the DA
The original digital signal and a signal whose phase is delayed by 18 Ts (Ts: sampling period) are input to the CI<30) and DAC2 (31). According to the circuit with such a configuration, as shown in the timing chart shown in FIG. 8, the output of the DA converter (31) is delayed by 18 Ts in phase with respect to the output of the DA converter (30), so that The signal shown in FIG. 5(C) showing the arithmetic average of each output is data obtained by superimposing linear interpolation data on the signal in FIG. 1(a). That is, the signal output from the operational amplifier (33) becomes twice oversampled data of the original signal.

(c) Problems to be Solved by the Invention According to the above-mentioned oversampling device, in addition to the DA converter, a circuit for creating a signal whose phase is delayed by '/lTs with respect to the original digital signal is required. Such circuits are relatively complex, and also have a significant increase in component count and cost. An object of the present invention is to configure an oversampling device by adding a simple circuit.

(d) Means for Solving the Problems In view of the above problems, the present invention provides an oversampling device that creates an oversampling signal by linear interpolation from a transmission signal in which the same digital data is transmitted twice repeatedly, a first DA converter to which the digital data is input and a signal that rises during one data period of the digital data is input as an activation signal; an inverter to invert the activation signal; and an inverter to which the digital data is input. and a second DA converter into which the output signal of the inverter is input as an operating signal, and a circuit for arithmetic averaging of the outputs of the first and second DA converters.

Furthermore, the oversampling device creates an oversampling signal by linear interpolation from a digital audio signal in which Lch and Rch signals are transmitted alternately, the digital data being input, and the Lch and Rch signals being transmitted alternately.
In response to the LRCK signal identifying the Lch and Rc
first and second DA converters that output h analog signals; an inverter that inverts the LRCK signal and outputs the LRCK signal; the digital data is input;
and the Lch and Rch in response to the LRCK signal.
third and fourth DA converters that output analog signals; a first averaging circuit that arithmetic averages the outputs of the first and third DA converters; and outputs of the second and fourth DA converters. and a second averaging circuit for arithmetic averaging.

(e) Effect According to the first configuration, among the digital data that is repeatedly transmitted twice from the first D and A converters, two analog data corresponding to the previous data are sent to the first D and A converters. It is output for only one time period. Further, the second DA converter outputs analog data corresponding to the latter data of the digital data for only two data periods. Therefore, the second D
The analog data output from the A converter is delayed in phase by l data period compared to the first DA converter.

Therefore, the analog data output from the circuit that arithmetic averages the analog data from the first and second DA converters is 1 data obtained by performing linear interpolation of the analog data output from the first DA converter. This is analog data that changes every period.

Furthermore, according to the second configuration, the Lch analog data output from the third DA converter is out of phase by 18 Ts compared to the Lch analog data from the first DA converter. Therefore, the Lch analog data output from the first averaging circuit is double oversampled data of the Lch analog data output from the first DA converter. Similarly, the Rch analog data output from the fourth DA converter is out of phase by 18 Ts compared to the Rch analog data from the second DA converter, so the Rch analog data output from the second averaging circuit
The analog data is the Rch from the second DA converter.
This becomes 2f sound oversampling data of analog data.

(f) Example Hereinafter, one embodiment of the present invention will be described using the drawings.

FIG. 1 is a circuit block diagram of this embodiment.

In the figure, (1) is a signal processing IC (LC7880 manufactured by Sanyo Electric Co., Ltd.), and two DA converters (
Built-in DACI, DAC2). Lch and Rch digital data is sent from pin 8 to signal processing IC (1”)
LR applied from pin 6 and pin 9
After being DA-converted in accordance with the CK signal and the BCL K signal (pit clock signal), it is output from pin 1 and bin 20 as Lch and Rch analog data. FIG. 2 shows a timing chart of the digital data, LRCK signal, and analog data input and output to and from the signal processing IC (1). As shown in the figure,
From pin 1 and bin 20 of signal processing 1c (1), Lch changes every sampling period defined by Ts.
%Rch analog data is output. Also, these Lc
h, Rch analog data is processed by waveform shaping circuits (2) (3).
), amplified by operational amplifiers (4) and (5), and then passed through low-pass filters (6) and (7).

R is output.

The circuit configuration described above is the same as the circuit configuration used in existing compact disc players and the like that do not use the oversampling technology according to the present application. The feature of this embodiment is that this circuit configuration includes a signal processing IC (1
'), an inverter (8) consisting of a transistor and a resistor
An oversampling device has been realized with a simple configuration that includes the following.

In the signal processing IC (1'), the BCLK signal and digital data are input to the 9th pin and the 8th pin, similar to the above signal processing IC (1).

Also, the above LRCK signal is connected to the 6th pin by the inverter (8).
The LRCK signal inverted by the LRCK signal is applied. or,
By applying the LRCK signal to the 6th pin, Rch and Lch analog data are output from the 1st pin and the 20th bin, respectively.

Figure 3 shows digital data, LRCK signal, Lch, Rch input and output to and from the signal processing IC (1').
It is a timing chart of analog data. As shown in the figure, the L output from the signal processing IC (1°)
The ch analog signal has a phase lead of 18 Ts compared to the Lch analog signal output from the signal processing IC (1), and the Rch analog signal output from the signal processing IC (1'). is the above signal processing tc(1)
The phase is delayed by 18 Ts compared to the Rch analog signal output from the Rch analog signal.

FIG. 4 is a timing chart showing the phase relationship between Lch and Rch analog data output from the signal processing IC (1) (1°). In the same timing chart, the symbols (1) (1°) after Lch and Rch indicate the respective symbols of the corresponding signal processing ICs. When the analog data of Lch (1) and Lch (1') shown in the same figure are arithmetic averaged, Lch (1) + L shown in the same figure is obtained.
A signal called ch(1') is created. Also, similarly Rc
When the analog data of h(1) and Rch(1') are arithmetic averaged, a signal Rch(1)+Rch(1') shown in the figure is created. Each of these signals becomes twice oversampled data of the analog data output from the signal processing IC (1'). The arithmetic average of Lch (1) and Lch (1') and Rch (1) and Rch (1') is performed by operational amplifiers (4) and (5), respectively. As described above, according to this embodiment, a double oversampling circuit can be constructed by simply adding a similar signal processing IC and an inverter to an existing signal processing circuit.

According to this embodiment, the analog signals output from Lch, Rch have a phase difference of 18 Ts as shown in FIG. 4, but this phase difference is extremely short in terms of time. , the phase shift is not an auditory problem. For example, like a compact disc, the sampling frequency fs is 44.
If the frequency is 1 KHz, this phase shift will reduce the speed of sound to 34
Assuming 0m/sec, 1/(88,2X10"X2)X340X10"-1,
911, and at the ear, the deviation is 1.9111111.

FIG. 5 is a diagram showing another embodiment of the present invention. The oversampling circuit of this embodiment has four DA converters (DACI to DAC
4') (9) (10) (11) (12), two AND gate circuits (13) (14), three inverters (15) (16) (17), and two operational amplifiers (1
8) (19) and resistance (20) (21) (22) (23
).

The DA converter converts 16-bit digital data into analog data each time it is input. Digital data is applied to the DATA input terminal and is taken into the DA converter one bit at a time each time a pit clock is applied to the DATA CLOCK input terminal. or,
The converted analog signal is output from this DA converter every time the signal applied to the LE input terminal is inverted from H level to L level. Further, the analog signal output in this manner is held as the output signal of the DA converter until the next analog signal is output.

The LRCK signal is applied to the LE input terminals of DACI (9) and DAC2 (10) via an inverter (15). Also, DAC3 (11) and DAC4 (12)
The LRCK signal is applied to the LE input terminal of , via two inverters (16) and (17). Also, DAC
The AND output of the pit clock (BCLK signal) and the LRCK signal is applied to the DATA CLOCK input terminal of I (9), and the DATA CLOCK input terminal of DAC2 (10)
A BCLK multiplied signal is applied to the CLOCK input terminal. Furthermore, an inverted signal of the LRCK signal (LRCK signal) is input to the DATA CLOCK input terminal of DAC3 (11).
AND output of BCLK signal is applied, and the DAC
4 (12) DATA CLOCK input terminal has BC.
LK signal is applied. And DAC1~4 (9
)(10),(11),(12) A digital data signal is input to the DATA input terminals. The outputs of DACI (9) and DAC4 (12) are both operational amplifiers (AMP 1
) (18), where it is arithmetic averaged. Further, the outputs of DAC2 (10) and DAC3 (11) are both applied to an operational amplifier (A M P2 ) (19), where they are arithmetic averaged. According to this embodiment configured as above, AMP 1 (18) and AMP 2 (
The output signal of 19) is twice oversampled L
It becomes an analog output signal of ch and Rch. This will be explained below using the timing chart shown in FIG.

The signal applied to the DATA input terminal of each DA converter is phase-aligned so that it becomes an Lch signal during the period when the LRCK signal is at H level, and becomes an Rch signal during the period when the LRCK signal is at L level. DATA of DAct(9)
Since the AND output of the LRCK signal and the BCLK signal is applied to the CLOCK input terminal, the sixth
As shown in Figure (c), BCL is used only during the Lch signal period.
A K signal is applied. Therefore, in DACI(9), Lc
h digital signals are sequentially DA-converted, and therefore analog signals corresponding thereto are created. Also, DACI (9)
Since the LRCK signal shown in Figure (b) is applied to the LE input terminal of DACI (9), the analog signal is output in response to the falling edge of this LRCK signal. ) is output.

The same signals are applied to each input terminal of the DAC2 (10) except for the BCLK signal applied to the DATA input terminal. Therefore, the output timing of the analog signal 0 outputted from the DAC2 (10) is the same as that of the above-mentioned DACI (9). However, the DATA of this DAC2 (10)
The BCLK signal applied to the CLOCK input terminal is
Unlike the case of the DACI (9), since the voltage is constantly applied, the Lch and Rch digital signals are alternately converted into analog signals in the DAC2 (10). However, since the fall timing of the LRCK signal that determines the output timing of the DAC2 (10) is immediately after the Rch digital signal is taken into the DAC2 (10), the Rch digital signal is Analog output from DAC2 (10) will be performed immediately after the signal is converted to analog, so the DA
An Rch analog signal as shown in FIG. 2(e) is output from C2 (10).

Among the signals applied to DAC3 (11) and DAC4 (12), the signal applied to the DATA input terminal is the same as the above DACI (9) and DAC2 (10), but the L
The signals applied to the E input terminal and the DATA CLOCK input terminal are different from those described above. Since the inverted signal of the LRCK signal, that is, the LRCK signal, is applied to the LE input terminal, the D
The output timing of the signals output from AC3 (11) and D A C4 (12) is the same as the above DACI (9) and D
It deviates by 18 Ts compared to AC2 (10).

Now, here is the DATA CLOC of DAC3 (11).
The AND output of the BCLK signal and the LRCK signal is applied to the K input terminal, but this AND output corresponds in timing to the period in which the Rch data signal is applied to the DATA input terminal of DAC3 (11), and this Therefore, DATA
The BCLK signal is intermittently applied to the CLOCK input terminal only for inputting and tanning Rch data. The application timing of this BCLK signal is shown in the same figure (h). Therefore, only the Rch digital data is taken into the DAC 3 (11), and therefore, the DAC 3 (11) converts only the Rch digital data into an analog signal. Therefore, from DAC3 (11), LRCK
In response to the falling edge of the signal, an analog signal of <Rch is output as shown in (i) of the same figure.

On the other hand, since the BCLK signal is always applied to the D A C4 (12), the Lch
, Rch digital signals are taken in, DA conversion is performed. However, since the fall timing of the LRCK signal, which determines the output timing of the analog signal, is immediately after the DA conversion is performed on the Lch digital data, the timing from DA C4 (12) is as shown in (j) in the same figure. , Lch analog signals are output.

In the above manner, DAC1 to 4 (9) (10) (11
)(12), Figure 6(d)(e)(i)(
An analog signal as shown in i) is output. Among these signals, the output signals from DACI (9) and DAC4 (12) are arithmetic averaged by AMP 1 (18) and output as a twice Lch oversampled signal as shown in (k) of the same figure. It is output from AMP 1 (18). In addition, the output signals from DAC2 (10) and DAC3 (11) are arithmetic averaged by AMP2 (19) and outputted as a double Rch oversampled signal as shown in FIG. 2 (2). is output from.

In the manner described above, Lch and Rch twice oversampled signals are created and output. The phases of these signals are shifted by 18 Ts as in the previous example, but as mentioned above, such a phase shift is such that it cannot be discerned audibly, so the phases are adjusted in the subsequent circuit. etc. is not necessary.

(G) Effects of the Invention As described above, according to the present invention, data can be oversampled by simply adding an inverter without adding a relatively complicated phase matching circuit or the like.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a timing chart of signals input and output to the signal processing IC (1) in the same embodiment, and FIG. 3 is a diagram showing signals in the same embodiment. FIG. 4 is a timing chart of signals input and output to and from the processing IC (1'); FIG. 4 is a timing chart of output signals in the same embodiment; FIG. 5 is a circuit block diagram showing another embodiment; FIG. 7 is a timing chart of signals in the same embodiment, FIG. 7 is a circuit block diagram showing a conventional example, and FIG.
The figure is a timing chart of signals in the conventional example. (I Ml')...Signal processing IC1 (4) (5)
(18) (19)...Operational amplifier (arithmetic average circuit)
, (8) (15) (16) (17)...inverter. 6. Ask TCIBCt for one plate book m-" 1111 plate plate m-"
1IIIIllIllllII+ (h) to BCL 11
Sarariichi” 11 books 1 plate m-” 1I 11 books LJ 11 books 1
■Book Figure 7

Claims (2)

[Claims] (1) An oversampling device that creates an oversampling signal by linear interpolation from a transmission signal in which the same digital data is repeated twice and transmitted, the digital data being input, and one of the digital data being transmitted. a first DA converter to which a signal that rises during the data period is input as an activation signal; an inverter for inverting the activation signal; and an inverter to which the digital data is input and an output signal of the inverter is input as the activation signal. a second DA converter, and the first and second D/A converters;
An oversampling device comprising a circuit that arithmetic averages the output of an A converter. (2) An oversampling device that creates oversampling data by linear interpolation from digital audio data in which Lch and Rch data are transmitted alternately, wherein the digital data is input and the Lch and Rch data are transmitted alternately.
first and second DAs that output the Lch and Rch analog data in response to an LRCK signal that identifies the channel;
converter and invert the LRCK signal @LRCK
an inverter that outputs the @signal; and an inverter to which the digital data is input, and in response to the @LRCK@ signal, the L
third and fourth DA converters that output ch and Rch analog data; a first averaging circuit that arithmetic averages the outputs of the first and third DA converters;
and a second averaging circuit that arithmetic averages the output of the fourth DA converter.