JPH02270432A - D-channel protocol multiplex processing system for isdn - Google Patents

Abstract

PURPOSE:To allow a single data link controller to execute processing at a data link layer of plural host layer controllers by providing a common memory between the data link controller and the host layer controller and using a flag register for hand-shake representing the access state to the common memory. CONSTITUTION:The system is provided with a common memory used for transmission reception of a data between host layer controllers 2, 3 and a data link layer controller 1, host layer flag registers 9, 10 representing the access state to the common memory 4 from the host layer controllers 2, 3 respectively, and a data link layer flag register representing the access state from the data link controller 1 to the common memory 4 and when the data link layer controller 1 gives the data processed thereby to the host layer controller, all host layer flag registers 9, 10 are read to confirm it that there is no access applied to the common memory. Thus, one data link controller controls plural links.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a D-channel protocol multiplexing method for ISDN.

[Conventional technology]

Conventionally, when processing the D channel protocol within a terminal connected at the reference point S of ISDN, only one data link layer controller was faced, and a serial interface was also used between the upper layer controller and the data link controller. I went there.

[Problem to be solved by the invention]

In the conventional D channel protocol processing method described above,
Although a plurality of links can be set on one D channel, one data link controller can control only one link, and data link controllers are required for the number of links required. If a serial interface is used between the data link controller and the upper layer controller, data transfer takes time and
Processing is required to prevent underruns and overruns when transmitting and receiving data.

[Means to solve the problem]

The ISDN D-channel protocol multiplexing method of the present invention is connected to the network at the ISDN reference point S,
a plurality of upper layer controllers that perform processing of upper layers higher than the network layer of the D channel protocol;
A data link layer controller that processes the data link layer of the D channel protocol, and a controller that is accessible from the upper layer controller and the data link controller and is used for data exchange between the upper layer controller and the data link layer controller. a shared memory, an upper layer flag register indicating an access state to the shared memory from each of the upper layer controllers, and a data link layer flag register indicating an access state to the shared memory from the data link controller; a bus transceiver that separates a bus to which the shared memory is connected and a bus to which the upper layer controller is connected except when accessing the shared memory from the upper layer controller; The data link layer controller includes a bus transceiver that separates a bus to which the data link layer controller is connected except when accessing the shared memory from the data link layer controller.

In this configuration, when data processed by the data link layer controller is handed over to the upper layer controller, the data link layer controller reads the flag registers of all the upper layers to ensure that the shared memory is not being accessed. If it is not being accessed, it waits, and if it is not being accessed, it writes to its own flag register that it will start accessing the shared memory, and connects the bus to the shared memory using its own bus transceiver. Loads the data to be transferred to the upper layer controller into the shared memory, separates the bus to the shared memory using its own bus transceiver, and specifies that access to the shared memory has ended and which upper layer controller will take over the data. After writing to the flag register of the data link layer and waiting for the upper layer controller to finish taking over, it reads the flag register of the specified upper layer controller intermittently. From the layer controller side, read the flag register of the data link layer, and if the load on the data link controller side is completed and the upper layer controller to take over is yourself, read the flag register of the other upper layer controller. Confirm that no upper layer controller is accessing the shared memory, and if it is, it will wait; if it is not, it will write to its own flag register to indicate that it will start accessing the shared memory. The bus transceiver connects the bus to the shared memory and receives data from the data link controller on the shared memory, and when finished, the bus transceiver on its own side separates the bus to the shared memory and finishes accessing the shared memory. The data link controller detects the completion of taking over the upper layer controller, writes the fact that there is no more upper layer controller to take over to its own flag register, and sends a message from the data link controller to its own flag register. Finish the handover to the upper layer controller.

Also, when passing data processed by the upper layer controller to the data link controller, the upper layer controller reads the flag registers of the data link controller and other upper layer controllers and accesses the shared memory. If it is not being accessed, it waits, and if it is not being accessed, it writes to its own flag register to indicate that it will start accessing the shared memory, and connects the bus to the shared memory using its own bus transceiver. Then, it loads the data to be transferred to the data link controller into the shared memory, and when it is finished, the bus transceiver on its own side separates the bus to the shared memory, and sends a message to the data link controller on the shared memory indicating that access to the shared memory has ended. After writing to its own flag register that there is data to be transferred and waiting for the completion of the transfer, it reads the flag register of the data link controller intermittently, and transfers data to the data link controller side. From then on, it reads the flag registers of all upper layers and confirms that the shared memory is not being accessed and that there is data to be delivered to the data link controller on the shared memory.If it is being accessed, it waits and if it is not being accessed, In this case, it writes to its own flag register that it will start accessing the shared memory, connects the bus to the shared memory using its own bus transceiver, receives data from the upper layer controller, and when finished, the own bus When the transceiver separates the bus to the shared memory and writes a message to its own flag register indicating that access to the shared memory has ended, the upper layer controller detects the end of data transfer from the data link controller and indicates that it should receive the data. A message indicating that there is no data is written to its own flag register, and the transfer from the upper layer controller to the data link controller is completed.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, in which there is one data link layer controller for eight upper layer controllers.

First, the data link layer controller (L2-CTL
) 1 to the upper layer controller (UL-CTL) 2 will be described. D-channel protocol physical layer controller (LL-CTL) 11 with an interface to the reference point S of the l5DN
The L2-CTLI, which has received the data from (REG) 9.10 sold for 8, check that MEM4 is not being accessed from anywhere, wait if it is being accessed, MEM4 if it is not being accessed.
Set the flag register REG to start accessing EM4.
Write to 8. L2 by bus transceiver (BT)5
- Connect the bus between CTLl and MEM4, and
Load the data to be transferred to TL2 from L2-CTLI to MEM4. Next, BT5 separates the bus between L2-CTLI and MEM4, and writes to REG8 that the access to MEM4 is finished and that UL-CTL2 will take over the data, and UL-CTL2 takes over the data. UL-CTL2 reads REG9 intermittently after a predetermined timing in order to wait for L2-CTLI to finish accessing MEM4, and UL-CTL2 reads REG8, and L2-CTLI has finished accessing MEM4. Make sure that you are the upper layer controller that should take over the REG
Read the flag registers of all upper layer controllers other than 9 and confirm that MEM4 is not being accessed from anywhere.If it is being accessed, make it wait, and if it is not being accessed, UL- to REG9. C.T.L.
2 writes information to start accessing the MEM.

B T 6 G: Therefore, UL-CTL2 and L2-CT
Connect the bus between LI and MEM4 to UL-CTL
Data from L2-CTLI is transferred to 2. Next, B.T.
6 separates the bus between UL-CTL2 and L2-CTLl, and sends RE to indicate that access to MEM4 has ended.
Write to G9. As a result, L2-CTLI, which is intermittently reading REG9, detects the end of receiving data from UL-CTL2, and reports that there is no longer an upper layer controller to receive data from L2-CTLI.
Write to EG8 and end the data transfer from L2-CTLI to UL-CTL2.

Next, a case will be described in which data is transferred from the upper layer controller LIL-CTL2 to the data link controller L2-CTLI. UL-CTL2, which has finished processing in the upper layer above the network layer, reads REG8 and the flag registers of upper layer controllers other than itself, confirms that there is no access to MEM4 from anywhere, and confirms that access is currently in progress. If so, wait, and if access is not in progress, UL-CTL2 writes to REG9 that it will start accessing MEM4. Br3 connects the bus between tJL-CTL2 and MEM4, and transfers the data from UL-CTL2 to L2-CTLl.
Load to EM4. Subsequently, UL-C by Br3
Separate the bus between TL2 and MEM4, and write information indicating that access to MEM4 has ended and L2-CTLI on MEM4.
Write to REG9 that there is data to be transferred to L2-C
After taking a predetermined timing to wait for TLI to finish receiving data, it reads REG8 intermittently. L2-CTLI goes to read the flag register (REG) 9.10 of all upper layer controllers and confirms that there has been no access to MEM4 from anywhere.
Confirm that there is data to be retrieved on M4, wait if it is being accessed, and send to L2-CT if it is not being accessed.
LI writes to REG8 that it will start accessing MEM4. Connect the bus between L2-CTLI and MEM4 by Br3 and take over the data from UL-CTL2 on MEM4 to L2-CTLI. Next, separate the bus between L2-CTLI and MEM4 by Br3. Then ME
Writes to REG8 that the access to M4 has ended.This causes the UL-C that is intermittently reading REG8
TL2 detects the end of data transfer from L2-CTLI and sends RE to indicate that there is no more data to transfer to MEM4.
Write to G9 and end the data transfer from UL-CTL2 to L2-CTLI.

Note that other upper layer controllers, such as UL-CT
The same can be done for L3 and L2-CTLI. Also,
By separating the data area from the data link controller to the upper layer controller on the MEMJ and the data area from the upper layer controller to the data link controller, data can be transmitted from both directions from the upper layer controller or from the data link controller. There is no problem even if these processes proceed at the same time.

〔Effect of the invention〕

As explained above, according to the present invention, a shared memory is provided between a data link controller and an upper layer controller, and a handshake flag register is used to indicate the access state of the data link controller and upper layer controller to the shared memory. This allows a single data link controller to perform processing in the data link layer of a plurality of upper layer controllers. That is, links to multiple upper layer controllers can be multiplexed on one data link controller. In addition, by using a parallel interface between the data link controller and the upper layer controller, high-speed data transfer is possible, and there is no risk of underruns or overruns that occur when using a serial interface, and there is no overhead for transferred data. can also be avoided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. 1... Data link layer controller, 2, 3...
- Upper layer controller, 4... shared memory, 5.
6.7... Bus transceiver, 8.9.10... Flag register, 11... Physical layer controller.

Claims (1)

[Claims] a plurality of upper layer controllers that are connected to the network at the reference point S of the ISDN and perform processing of upper layers higher than the network layer of the D channel protocol; a data link layer controller that performs processing of the data link layer of the D channel protocol; A shared memory that is accessible from the upper layer controller and the data link controller and is used for data exchange between the upper layer controller and the data link layer controller, and a shared memory that is accessible from each of the upper layer controllers to the shared memory. an upper layer flag register indicating an access state; a data link layer flag register indicating an access state from the data link controller to the shared memory; a bus to which the shared memory is connected; and a bus to which the upper layer controller is connected. and a bus transceiver that separates the upper layer controller from the shared memory except when accessing the shared memory;
A bus transceiver that separates a bus to which the shared memory is connected and a bus to which the data link layer controller is connected except when accessing the shared memory from the data link layer controller. D channel protocol multiple processing method.