JPH022714A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To limit the amplitude of an input signal to an inverter circuit to a degree contained by its transition region by setting the inverter circuit having comparatively large capability and two current sources which charge or discharge the input capacitance of the circuit selectively according to an internal output signal as an output circuit. CONSTITUTION:The inverter circuit N1 for driving output for the output circuit is provided in series between a source voltage VDD and ground potential VSS, and it is constituted of a pair of P-MOSFETs Q1 and Q2 and a pair of N- NOSFETs Q11 and Q12. As the input terminal of the circuit N1, a capacitor C1 is provided between a node n1 and the ground potential VSS of the circuit, and the capacitor C1 is formed with the gate capacitance of the FETs Q1 and Q2 and that of the FETs Q11 and Q12, and a prescribed voltage Vc1 is supplied to the gate of the FETQ1, and a corresponding internal output voltage d0 is supplied from a fast logical integrated circuit to the gate of the FFTQ2. And the FETQ1 functions as a constant current source, and the FETQ2 is turned on selectively according to the output signal d0, and a de-charge circuit can be formed by the FETs Q11 and Q12 provided between the node n1 and a voltage supply point V2.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a semiconductor integrated circuit device, and can be used, for example, in a semiconductor integrated circuit device having a plurality of output circuits (output cover sofas) that are activated at the same time. It is about effective techniques.

[Conventional technology]

There is a high-speed logic M circuit whose basic configuration is a 0MO3 (complementary MO5>logic gate circuit). A high-speed logic integrated circuit includes a plurality of output circuits that have a relatively large driving capacity and are activated simultaneously.

Regarding the output circuit, for example, Japanese Patent Application No. 61-06572
It is described in No. 9 etc.

[Problem to be solved by the invention]

In the above-described high-speed logic integrated circuit, a plurality of output circuits having a relatively large driving capacity are simultaneously activated, so that a relatively large current is intermittently passed through the power supply voltage supply line or the ground potential supply line. A relatively large resistive load or inductive load is coupled to these power supply voltage supply line and ground potential supply line. For this reason, multiple output circuits are activated at the same time, and a relatively large current is intermittently passed through the power supply voltage supply line or ground potential supply line, causing non-negligible noise in the power supply system of high-speed logic integrated circuits. is induced. These noises cause malfunctions of the output circuit of the high-speed logic integrated circuit or its peripheral circuits.

As one means for dealing with this, a current control type output circuit as shown in FIG. 4 has been proposed. In the same figure, P-channel MO3FETQ5 and N-channel MO3FETQ5
The O3FETQI 5 constitutes an inverter circuit for output driving, which inverts the internal output signal dO and sends it out via the data output terminal DO. A predetermined constant voltage Vcl is connected to the gate between MO3FETQ5 and the circuit power supply voltage DD.
P channel M functions as a constant current source by receiving
O3FETQ4 is provided. Also, MO3FETQ1
5 and the circuit ground potential Vss is provided an N-channel MO3FETQ14 which functions as a constant current source by receiving a predetermined constant voltage Vc2 at its gate. As a result, the level change of the output signal sent out via the data output terminal DO is caused by MOS FETQ4 or Q14
The current value is limited according to the current value of the constant current source consisting of. As a result, a plurality of output circuits are brought into operation at the same time, so that current changes occurring in the power supply voltage supply line and the ground potential supply line are suppressed, and malfunctions of the output circuit of the high-speed logic integrated circuit or its peripheral circuits can be prevented.

However, these current-controlled output circuits have the following disadvantages due to their limited driving ability:
That is, as mentioned above, the current controlled output circuit has M
A constant current source consisting of O3FETs Q4 and Q14 is provided, and its driving capability, that is, its output current is limited. Therefore, the output impedance of the output circuit becomes relatively high, the high level and low level of the output signal are compressed, the level margin of the output signal is reduced, and the output against external noise transmitted via the output signal line The absorbing power of the circuit decreases.

An object of the present invention is to provide an output circuit that can suppress changes in the level of an output signal without reducing the level margin of the output signal and without reducing the ability to absorb external noise. Another object is to suppress power system noise and prevent malfunctions while avoiding an increase in the chip area of a semiconductor integrated circuit device that includes a plurality of output circuits that are activated at the same time.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows. That is,
The output circuit is configured by an inverter circuit with a relatively large driving capacity and two current sources that selectively charge or discharge the input capacitance of the inverter circuit according to an internal output signal, and the amplitude of the input signal of the inverter circuit is is limited to an extent that can include the transition fa region.

[For production]

According to the above means, the output signal level can be increased without reducing the drive capability of the inverter circuit, in other words, without reducing the level margin of the output signal of the output circuit (and without reducing the absorption capacity for external noise). As a result, noise in the power supply system of a high-speed logic integrated circuit including a plurality of output circuits that are activated at the same time can be reduced and malfunction thereof can be prevented.

[Embodiment 1] FIG. 1 shows a circuit diagram of an embodiment of an output circuit to which the present invention is applied. The output circuit of this embodiment is included in a high-speed logic integrated circuit whose basic configuration is a CMO3 logic gate circuit, although it is not particularly limited. The high-speed logic integrated circuit includes a plurality of output circuits that have the same circuit configuration as the output circuit of FIG. 1 and are activated at the same time, and a large number of CMO3 logic gate circuits, and each circuit element of FIG. Together with other circuit elements (not shown) of the high-speed logic integrated circuit, it is formed on a single semiconductor substrate, such as, but not limited to, single crystal silicon. In the figures below, a MOS FET whose channel (back gate) part is marked with an arrow is a P-channel type, and is shown to be distinguished from an N-channel MO3FET whose channel (back gate) part is not marked with an arrow.

Although not particularly limited, the output circuit of this embodiment receives an internal output signal do transmitted from another circuit (not shown) of the high-speed logic integrated circuit, and sends it to the outside via a corresponding data output terminal DO. As described above, a high-speed logic integrated circuit includes a plurality of output circuits having the same circuit configuration, and a similar internal output signal is supplied to each output circuit. These internal output signals are formed simultaneously according to timing signals (not shown), resulting in simultaneous state transitions of the plurality of output circuits.

In FIG. 1, the output circuit includes an inverter circuit N1 for output driving.This inverter circuit N1 includes, but is not particularly limited to, a pair of 0MO3, that is, a pair of inverter circuits provided in series between the power supply voltage van of the circuit and the ground potential Vss. P channel MOS FET and N channel MO3FE
Let T be the basic configuration.

These MOS FETs are designed to have relatively large conductance. Thereby, the inverter circuit Nl is made to have a relatively large driving capacity.

An input terminal of the inverter circuit N1 is a node nl. Between this node n1 and the circuit ground potential Vsa,
A capacitor C1 is provided. In this embodiment, the capacitor C1 is the input capacitance of the inverter circuit N1, that is, the P-channel MOS FET and the N-channel M
This is realized by the gate capacitance of O3FET.

Between the node n1 and the voltage supply point Vl (first voltage supply point), there is a P-channel type (first conductivity type) MOSFET QI (first) MOS FET, which is not particularly limited.
) and Q2 (second (7) MOSFET). A predetermined constant voltage Vcl is supplied to the gate of MOSFETQI, and MO3! A corresponding internal output signal dO is supplied to the gate of ETQ2 from a circuit (not shown) of the high-speed logic integrated circuit. As a result, M
OSFETQI functions as a constant current source, and MOS FETQI functions as a constant current source.
ETQ2 is selectively turned on according to internal output signal dO. On the other hand, between node n1 and voltage supply point v2 (second voltage supply point), there are N-channel type (second conductivity type) MO3FET QII (third MOSFET) and Q12 (fourth MOSFET). A predetermined constant voltage Vc2 is supplied to the gate of 0M03FETQI 1 provided with a discharge circuit, and MOSFETQI 2
The internal output signal dO is supplied to the gate of . As a result, MOSFET QI 1 functions as a constant current source, and MOSFET QI 2 is selectively turned on according to internal output signal do.

Here, the internal output signal dO is not particularly limited, but when it is set to logic 0°, it is set to a low level like the ground potential Vss of the circuit, and when it is set to logic 1, it is set to a low level similar to the circuit power supply voltage VDD. This is a MOS level signal that is set to a high level. Moreover, the constant voltages Vcl and VC2 are
As described below, the corresponding MOSFETQI and Qll
A predetermined voltage value is set such that the capacitor C1 can function as a constant current source that supplies a predetermined charge current or discharge current to the capacitor C1. Further, voltage supply points v1 and v2 are supplied with predetermined voltages v1 and v2, respectively, such that the input signal of the node nl, that is, the inverter circuit Nl, covers its transition region and has a sufficiently small signal amplitude, although this is not particularly limited. be done.

FIG. 2 shows a signal waveform diagram of one embodiment of the output circuit of FIG. 1. Hereinafter, an outline of the operation of the output circuit of this embodiment will be explained with reference to FIG. 2 and the above-mentioned FIG. 1.

In FIG. 2, the internal output signal dO is at the circuit ground potential V
When it is set to low level like ss, MOSFETQ
MOSFET QI2 is turned on, and MOSFETQI2 is turned off. At this time, capacitor C1 is MOSFETQ
The node n1 is charged through I and Q2, and the node n1 eventually reaches a high level such as the voltage V1. Here the voltage
1 is a high level in the transition region of the input signal of the inverter circuit N1, that is, a voltage slightly higher than the input voltage va at which the output signal of the inverter circuit N1 begins to transition from a low level to a high level. As a result, inverter circuit N1
The output signal of , that is, the potential of the data output terminal DO is set to a low level like the ground potential Vss of the circuit.

When the internal output signal dO is changed from a low level such as the circuit ground potential Vss to a high level such as the circuit power supply voltage vno, when the level exceeds the voltage Vb'', the MOSFET QI 2 is turned on. MO3FE
TQ2 is turned off.

Therefore, capacitor CI is discharged via MOSFETs QIl and Q12. As a result, the potential of node n1 is gradually lowered according to the current value of the constant current source made of MOSFET QI1, and finally the voltage V2
It becomes a low level like . Here, the voltage V2 is set to a low level in the transition region of the input signal of the inverter circuit Nl, that is, a voltage slightly lower than the input voltage vb at which the output signal of the inverter circuit Nl starts to transition from a high level to a low level.

As the potential of the node n1 falls below the high level va of the transition region and is further gradually lowered, the output signal of the impark circuit N1, that is, the potential of the data output terminal DO, becomes
It gradually rises and finally reaches a high level like the circuit power supply voltage vI)D.

That is, in the output circuit of this embodiment, the discharge circuit for the capacitor C1 includes a constant current source made of a MOS FETQll, so that the potential of the node n1 is gradually lowered, and as a result, the output signal of the inverter circuit N1 becomes low level. It will gradually change from high level to high level.

Next, when the internal output signal dO is changed from a high level, such as the power supply voltage VD of the circuit, to a low level, such as the ground potential Vss of the circuit, its level becomes lower than the voltage va'. MO3FETQ2 turns on and MOSFETQI 2 turns off. Therefore,
Capacitor C1 is charged again via MOSFETs QI and Q2. As a result, the potential of the node n1 is gradually raised in accordance with the current value of the constant current source made of MOSFET QI, and finally reaches a high level such as the voltage v1.

The potential of the node n1 exceeds the low level vb of the transition region and gradually increases (as a result, the inverter circuit N1
The output signal of , that is, the potential of the data output terminal Do gradually decreases and finally reaches a low level similar to the ground potential Vss of the circuit. In other words, in the output circuit of this example,
The charge circuit for capacitor C1 is MOSFETQ
By including the constant current source made of I, the potential of the node nl is gradually increased, and as a result, the output signal of the inverter circuit N1 is gradually changed from high level to low level.

By the way, by relatively slowly changing the output signals of the plurality of inverter circuits N1, which are activated simultaneously, from a low level to a high level or from a high level to a low level according to the corresponding internal output signal do, high-speed logic integration is possible. Current changes in the circuit's power supply voltage supply line and ground potential supply line are relatively small.Therefore, relatively large resistive or inductive loads are placed on these power supply voltage supply lines and ground potential supply lines. Despite being coupled, noise in the ts source system generated by current changes is suppressed, and malfunctions of the output circuit of the high-speed logic integrated circuit and its peripheral circuits are prevented.On the other hand, the input of node n1, that is, the inverter circuit Nl The amplitude of the signal is, as described above, limited to the voltages v1 and v2 supplied to the voltage supply points v1 and v2, and these voltages v1 and v2 encompass the transition region of the input voltage R of the impark circuit N1. Moreover, the level difference is made to be sufficiently small.Therefore, the level change of the input signal of the inverter circuit N1 is accurately controlled, and the output No. 16 of the output circuit is made to transition with a desired transmission delay time. .

As described above, the output circuit of this embodiment is a relatively large FIA! A CM a S inverter circuit N1 having l1IJtp2 power, and a capacitor C provided between the input terminal of the inverter circuit Nl and the ground potential Vss of the circuit.
1, between the input terminal of the inverter circuit N1, that is, the node n1, and the voltage supply point Vl, there is a MOS FETQ 1 which functions as a constant current source by supplying a predetermined constant voltage Vcl to its gate; A MOSFET Q2 which receives an internal output signal 5)do at its gate is provided in series. Furthermore, between the node n1 and the voltage supply point v2, there is an MO3FET QI1 which functions as a constant current source by supplying a predetermined constant voltage Vc2 to its gate;
A MOSFE which receives the above internal output signal do at its gate.
TQ12 is provided in series form. Therefore, when the internal output signal do is changed from a low level to a high level or from a high level to a low level, the potential of the node nl is gradually changed according to the current value of the constant current source consisting of MO3FETs QI and Qll. , and the signal amplitude is made small enough to include the transition region. As a result, the level JL/change of the output signal of the inverter circuit Nl is accurately controlled, and the transition occurs with a predetermined transmission delay time. As a result, the noise level induced in the power supply system of high-speed logic integrated circuits and the like is suppressed, and malfunction thereof is prevented.

[Embodiment 2] FIG. 3 shows a diagram P3 of another embodiment of the output circuit to which the present invention is applied. The output circuit of this embodiment basically follows the embodiment of FIG. 1 above, and includes the inverter circuit N2 and capacitor C2 of FIG.
correspond to the inverter circuit N1 and capacitor C1 of FIG. 1 as they are. Further, the internal output signal do and the voltages v1 and V2 are formed under the same conditions as the internal output signal dO and the voltages v1 and v2 shown in FIG. 1, respectively. Hereinafter, explanations will be added regarding parts that are different from the embodiment shown in FIG.

In Figure 3, the output circuit has voltage supply points ■1 and ■2.
P-channel MO3FETQ provided in series between
3 and N channel MO3FETQ13. These MO3FETs Q3 and Q13 are connected to the above voltages Vl and v
A single CMOS inverter circuit is constructed using the circuit 2 as an operating power supply. The gates of the MO3FETs Q3 and Q13 are commonly coupled, and an internal output signal dO is supplied from a circuit (not shown) of the high-speed logic integrated circuit. Further, the commonly coupled drains of MO3FETs Q3 and Q13 are coupled to node n2 via resistor R1. Here, the resistor R1 is MO
Together with 3FETQ3, it constitutes a charge circuit for capacitor C2, and together with MOSFETQ13, it constitutes a discharge circuit for capacitor c2. Therefore, the resistor R1 is designed to have a predetermined resistance value such that the level of the node n1 is raised and lowered at a desired speed.

When the internal output signal do is set to a low level such as the ground potential Vss of the circuit, MO3FETQ3 is turned on and MO3FETQI3 is turned off. At this time, capacitor C2 is connected to MO3FETQ3 and resistor R1.
is charged via the node n2, and finally the voltage v1
It is considered to be a high level such as. By setting the node n2 to a high level like the voltage v1, the inverter circuit N2
The output signal of , that is, the data output terminal DO is set to a low level like the ground potential Vss of the circuit.

When the internal output signal do is changed from a low level such as the circuit ground potential Vss to a high level such as the circuit power supply voltage VDD, the MO3FETQ3 is turned off,
Instead, MO3FETQI 3 is turned on. Therefore, capacitor C2 is discharged via MO3FET Q13 and resistor R1. As a result, the potential of the node n2 is gradually lowered at a predetermined speed determined by the resistor R1, and is finally brought to a low level such as the voltage v2. By making the potential of node n2 lower than the high level of its transition region and further lowering it gradually, the output signal of inverter circuit N2 is slowly transitioned from low level to high level, and finally the power supply voltage V of the circuit
It is considered to be at a high level such as OO.

Next, when the internal output signal dO is changed from a high level such as the circuit power supply voltage Voo to a low level such as the circuit ground potential Vss, MO3FETQ13 is turned off, and MO3FETQ3 is turned on again. It is said that Therefore, capacitor C2 is MO3FETQ
3 and the resistor R1. This results in
The potential of the node n2 is gradually increased at a predetermined speed determined by the resistor R1, and is finally brought to a high level such as voltage 1. As the potential of the node n2 exceeds the low level of the transition region and is further gradually raised, the output signal of the inverter circuit N2 is slowly transitioned from high level to low level, and finally reaches a low level such as the ground potential Vss of the circuit. It is said that That is, in the output circuit of this embodiment, since the charge circuit and discharge circuit for the capacitor C2 commonly include the resistor R1 having a predetermined resistance value, the level change of the node n2 is suppressed, and as a result, the change in the level of the inverter circuit N2 is suppressed. This suppresses level changes in the output signal.

As described above, the output circuit of this embodiment has a voltage supply point v
P-channel MO3FETQ3 and N are provided in series between 1 and 2 to form a CMOS inverter circuit.
These (7), including channel MOS FETQ13
) The above-mentioned M
A resistor R1 is provided, which together with the O3FET Q3 constitutes a charge circuit for the capacitor C2, and together with the MO3FET QI 3 constitutes a discharge circuit for the capacitor C2. The resistor R1 is configured to have a predetermined resistance value such that the potential of the node n2 is gradually raised or lowered with a predetermined slope. Further, the voltages v1 and (2) supplied to the voltage supply points v1 and v2 are made to include the transition region of the input signal of the inverter circuit N2 and have a sufficiently small level difference, as in the embodiment shown in FIG. be made into Therefore, when the internal output signal do is changed from a low level to a high level or from a high level to a low level, the potential of the node n2 is gradually changed at a predetermined speed, and as a result, the output signal of the inverter circuit N2, that is, the output circuit level changes are suppressed. This results in
Although the output circuit of this embodiment has a relatively simple circuit configuration, it has the same effects as the embodiment of FIG. 1 described above.

As shown in the above two embodiments, when the present invention is applied to an output circuit included in a semiconductor integrated circuit device such as a high-speed logic integrated circuit, the following effects can be obtained. (1) By configuring the output circuit with an inverter circuit with a relatively large driving capacity and two current sources that selectively charge or discharge the input capacitance of the inverter circuit according to an internal output signal, the inverter circuit Since the change in the level of the input signal can be suppressed, it is possible to suppress the change in the level of the output signal without increasing the chip area or reducing the driving ability of the inverter circuit.

(In paragraphs 21 and 41 (1), by making the amplitude of the input signal of the impark circuit sufficiently small to include its transition region, the capacitor charging or discharging time can be accurately controlled. is obtained.

(3) - According to the above (11) and (2), the ability to absorb external noise is reduced without reducing the drive capability of the inverter circuit, or in other words, without reducing the level margin of the output signal of the output circuit. without any
This provides the effect of accurately suppressing level changes in the output signal.

(4) Items (1) to (3) above provide the effect of reducing power supply noise and preventing malfunctions of high-speed logic integrated circuits that include a plurality of output circuits that are activated at the same time.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and it should be noted that various changes can be made without departing from the gist of the invention. For example, in FIG. 1, MO5FETs Q1, Q2 and Qll, Q12 are all P-channel MOS FETs or N-channel M
It can be configured by O3FET. in this case,
It is necessary to supply the inverted signal of the internal output signal dO to the gate of MOS F E, TQ 2 or Q12, and the constant voltages Vcl and Vc2 are also connected to these MOS FEs.
It is necessary to select the value according to the conductivity type of T. In FIGS. 1 and 3, capacitors C1 and C2 are
Instead of the input capacitance of the inverter circuit Nl or N2, separate capacitance means having a predetermined capacitance may be used. In addition, the inverter circuits N1 and N2 are CMO
It does not need to be an S inverter circuit. In these embodiments, the voltages v1 and v2 may be selectively supplied to the voltage supply points ■1 and ■2 according to the output control signal, or the voltages v1 and v2 may be supplied instead of these voltages ■1 and V2. The power supply voltage VOO and the ground potential Vss of the circuit may be respectively supplied. Furthermore, the specific circuit configuration of the output circuit shown in FIGS. 1 and 3 can take various embodiments.

In the above explanation, the invention made by the present inventor was mainly applied to the output circuit of a high-speed logic integrated circuit, which is the background application field, but the invention is not limited thereto. The present invention, which can also be applied to gate array integrated circuits whose basic configuration is gate circuits, various semiconductor memory devices, etc., is widely applicable to semiconductor integrated circuit devices having a plurality of output circuits that are activated at least simultaneously.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, the output circuit is constituted by an inverter circuit with a relatively large driving capacity and two current sources that selectively charge or discharge the input capacitance of the inverter circuit according to an internal output signal, and the input signal of the inverter circuit is By making the amplitude sufficiently small to include the transition region, an increase in the chip area can be avoided and the drive capability of the inverter circuit can be maintained.
In other words, changes in the level of the output signal can be accurately suppressed without reducing the level margin of the output signal and without reducing the ability to absorb external noise. This makes it possible to reduce power supply noise and prevent malfunctions of high-speed logic integrated circuits that include a plurality of output circuits that are activated at the same time.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of an output circuit to which this invention is applied. FIG. 2 is a signal waveform diagram showing an embodiment of the output circuit of FIG. 1. FIG. 3 is a circuit diagram showing an embodiment of the output circuit of FIG. FIG. 4 is a circuit diagram showing another embodiment of an output circuit in which the same type of output circuit is used. N1. N2...Inverter circuit, Q1-Q5...P
Channel MO3FE'! '%Qll~Q15-N channel MO3FET, CI, C2...capacitor, R
1...Resistance. Figure ■1 ■2 SS Figure ss

Claims (1)

[Claims] 1. An inverter circuit for output driving, a capacitor provided between the input terminal of the inverter circuit and the ground potential of the circuit, and a capacitor that is selectively put into an operating state according to a corresponding internal output signal, and the above-mentioned A semiconductor integrated circuit device comprising: an output circuit including a charge circuit that charges a capacitor; and a discharge circuit that is activated in a complementary manner to the first current source and discharges the capacitor. 2. The charge circuit includes a first MO of a first conductivity type that is provided in series between a first voltage supply point and an input terminal of the inverter circuit and receives a first constant voltage at its gate.
The discharge circuit is configured of an SFET and a second MOSFET of the first conductivity type that receives the internal output signal at its gate, and the discharge circuit is provided in series between the second voltage supply point and the input terminal of the inverter circuit. a third MOS of a second conductivity type which receives a second constant voltage on its gate;
A second FET and a second one receiving the internal output signal at its gate.
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is constituted by a fourth conductive type MOSFET, and the capacitor is constituted by an input capacitance of the inverter circuit. 3. The potentials of the first and second voltage supply points are made to include the transition region of the input signal of the inverter circuit and have a sufficiently small level difference compared to the power supply voltage and ground potential of the circuit. A semiconductor integrated circuit device according to claim 1 or 2, characterized in that: