JPH02272736A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPH02272736A
JPH02272736A JP9561989A JP9561989A JPH02272736A JP H02272736 A JPH02272736 A JP H02272736A JP 9561989 A JP9561989 A JP 9561989A JP 9561989 A JP9561989 A JP 9561989A JP H02272736 A JPH02272736 A JP H02272736A
Authority
JP
Japan
Prior art keywords
conductive film
aluminum
semiconductor device
wiring
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9561989A
Other languages
Japanese (ja)
Inventor
Kazuhiko Katami
形見 和彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP9561989A priority Critical patent/JPH02272736A/en
Publication of JPH02272736A publication Critical patent/JPH02272736A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、半導体装置の配線の製造方法に関す〔従来の
技術] 従来の半導体装置の配線は、一般的に第3図に示すよう
にアルミニウムーシリコン合金でできていた。このとき
、アルミニウムーシリコン合金は加工性がよく、一般的
なドライエツチング技術で比較的寸法精度良く配線化す
ることができていた。
[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a method of manufacturing wiring for a semiconductor device [Prior Art] The wiring for a conventional semiconductor device is generally as shown in FIG. Made of aluminum-silicon alloy. At this time, the aluminum-silicon alloy had good workability, and it was possible to form wiring with relatively high dimensional accuracy using common dry etching techniques.

しかしながら近年の半導体集積回路の高集積化にともな
い、アルミニウムーシリコン合金よりも低抵抗で、しか
もマイグレーション耐性の強い配線材料が望まれるよう
になってきた。
However, as semiconductor integrated circuits have become more highly integrated in recent years, there has been a demand for wiring materials that have lower resistance than aluminum-silicon alloys and are more resistant to migration.

[発明が解決しようとする課題] アルミニウム合金よりも低抵抗で、マイグレーション耐
性の強い配線材料として、鋼などが挙げられるが、これ
らの金属はいれも加工性が悪く、既存ドライエツチング
技術では容易にエツチングできず、配線化することが非
常に困難であった。
[Problem to be solved by the invention] Steel is an example of a wiring material that has lower resistance than aluminum alloy and is more resistant to migration, but these metals have poor processability and cannot be easily processed using existing dry etching techniques. It could not be etched and it was extremely difficult to make wiring.

そこで本発明は、このような課題を解決しようとするも
ので、アルミニウム合金よりも低抵抗で、マイグレーシ
ミン耐性の強い配線材料である鋼などを容易に配線化す
る事ができる半導体装置の製造方法を提供するものであ
る。
Therefore, the present invention aims to solve such problems, and provides a method for manufacturing a semiconductor device that allows easy wiring of steel, which is a wiring material that has lower resistance than aluminum alloy and is highly resistant to migration. It provides:

[課題を解決するための手段] 本発明の半導体製造装置は、半導体基板上方に形成され
た第一の絶縁膜上の全面に第一の導電膜を形成する工程
、前記第一の導電膜上の予め設計された領域に第二の絶
縁膜を形成する工程、前記第一の導電膜上の前記第二の
絶縁膜におおわれていない領域に第二の導電膜を選択的
に形成する工程、前記第二の絶縁膜を除去する工程、前
記第二の導電膜をマスクとして前記第一の導電膜を選択
的に除去する工程より成ることを特徴とする。
[Means for Solving the Problems] The semiconductor manufacturing apparatus of the present invention includes a step of forming a first conductive film on the entire surface of a first insulating film formed above a semiconductor substrate, and a step of forming a first conductive film on the entire surface of a first insulating film formed above a semiconductor substrate. a step of forming a second insulating film in a pre-designed region of the first conductive film; a step of selectively forming a second conductive film in a region not covered with the second insulating film on the first conductive film; The method is characterized by comprising a step of removing the second insulating film, and a step of selectively removing the first conductive film using the second conductive film as a mask.

[実施例] 第1図は、本発明の半導体装置の製造方法により製造さ
れた半導体装置の構造を示す断面図である。すなわち、
本発明により得られるアルミニウムーシリコン合金10
3と銅105の二層より成る構造を有する配線を示して
いる。
[Example] FIG. 1 is a cross-sectional view showing the structure of a semiconductor device manufactured by the method of manufacturing a semiconductor device of the present invention. That is,
Aluminum-silicon alloy 10 obtained by the present invention
3 shows a wiring having a two-layer structure of copper 105 and copper 105.

第2図は本発明の半導体装置の製造方法の実施例を示す
工程断面図である。以下、工程順に詳細に説明していく
FIG. 2 is a process sectional view showing an embodiment of the method for manufacturing a semiconductor device of the present invention. The steps will be explained in detail below.

最初に、第2図(a)に示すように、半導体基板101
上方に形成されている酸化珪素膜102上の全面に第一
の導電膜としてアルミニウムーシリコン合金103をス
パッタリングにより1000人形成する。
First, as shown in FIG. 2(a), a semiconductor substrate 101
An aluminum-silicon alloy 103 is formed as a first conductive film on the entire surface of the silicon oxide film 102 formed above by sputtering.

次に、第2図(b)に示すように、アルミニウムーシリ
コン合金103上の配線とはならない領域にのみ第二の
絶縁膜として、フォトレジストレジスト104を100
00人形成する。このとき配線とならない領域にのみ絶
縁膜を形成するには、アルミニウムーシリコン合金10
3上に全面的に塗布されたフォトレジスト104をフォ
トリソ技術により配線となるように設計された領域だけ
を除去すればよい。
Next, as shown in FIG. 2(b), a photoresist resist 104 with a film thickness of 100% is applied as a second insulating film only to areas on the aluminum-silicon alloy 103 that will not become wiring.
Form 00 people. At this time, in order to form an insulating film only in areas that will not become wiring, aluminum-silicon alloy 10
It is only necessary to remove the photoresist 104 coated over the entire surface of the photoresist 104 by photolithography in only the area designed to become the wiring.

次に、第2図(C)に示すように、フォトレジスト10
4でおおわれていない領域、すなわち、配線となるよう
に設計された領域のアルミニウムーシリコン合金103
上にのみ選択的に第二の導電膜として1i105を形成
する。このとき銅105は鍍金技術によりアルミニウム
ーシリコン103合金上にのみ選択的に形成した。この
ときの銅105の膜厚は6000人であった。
Next, as shown in FIG. 2(C), a photoresist 10
Aluminum-silicon alloy 103 in the area not covered by 4, that is, the area designed to become wiring
1i105 is selectively formed as a second conductive film only on top. At this time, copper 105 was selectively formed only on the aluminum-silicon 103 alloy by plating technology. The film thickness of the copper 105 at this time was 6000.

銅の比抵抗はアルミニウムの比抵抗の約60%なので、
同一線幅の配線で同じ電流容量を得ようとする場合には
膜厚はアルミニウムの場合の60%でよい。
The specific resistance of copper is about 60% of that of aluminum, so
When trying to obtain the same current capacity with wiring of the same line width, the film thickness may be 60% of that of aluminum.

次に、第2図(d)に示すように、フォトレジスト10
4を除去する。
Next, as shown in FIG. 2(d), a photoresist 10
Remove 4.

最後に、第2図(e)に示すように、銅105をマスク
としてアルミニウムーシリコン合金103をドライエツ
チングにより除去する。ドライエツチングは三塩化はう
素(BCl2)、塩素(Cl 2)を主成分とする混合
ガスを用いて行い、この条件では1jl105はほとん
どエツチングされない。
Finally, as shown in FIG. 2(e), the aluminum-silicon alloy 103 is removed by dry etching using the copper 105 as a mask. Dry etching is performed using a mixed gas containing boron trichloride (BCl2) and chlorine (Cl2) as main components, and under these conditions 1jl105 is hardly etched.

なお、本実施例では第一の導電膜としてアルミニウムー
シリコン合金を用いているが、エツチングで容易に除去
できる導電膜ならなんでもよく、例えば、タングステン
、モリブデン、窒化チタン、チタンタングステンなどの
高融点金属あるいは高融点金属化合物を用いてもよい。
Note that although an aluminum-silicon alloy is used as the first conductive film in this example, any conductive film that can be easily removed by etching may be used. For example, high-melting point metals such as tungsten, molybdenum, titanium nitride, and titanium-tungsten Alternatively, a high melting point metal compound may be used.

さらに、本実施例では、第一の導電膜は単層となってい
るが、上述の導電膜のいくつかの組み合せによる多層膜
であってもよい。
Further, in this embodiment, the first conductive film is a single layer, but it may be a multilayer film consisting of a combination of some of the above-mentioned conductive films.

また、第二の導電膜は第一の導電膜上に選択的に成長さ
せられる導電体であれば何でもよく、鋼販外に、例えば
、金、クロム、ニッケルなどが考えられる。
Further, the second conductive film may be any conductive material as long as it can be selectively grown on the first conductive film, and in addition to steel, for example, gold, chromium, nickel, etc. can be considered.

また、第二の絶縁膜としては、フォトレジストの代わり
に酸化珪素膜、窒化膜などの無機物を用いてもよい。
Further, as the second insulating film, an inorganic material such as a silicon oxide film or a nitride film may be used instead of the photoresist.

[発明の効果] 以上述べたように、本発明によれば、酸化珪素膜上に全
面的に形成されたエツチングの容易なアルミニウムーシ
リコン合金上の予め設計された領域に選択的にエツチン
グが困難な銅を形成し、銅をマスクとしてアルミニウム
ーシリコン合金をエツチング除去する事により、エツチ
ングで除去することが困難な銅を有する多層構造の配線
を容易に得ることができ、アルミニウムーシリコン合金
単層の配線よりも、低抵抗で、しかもマイグレーション
に8fflい配線が容易に形成できるようになり、高信
頼性の半導体装置を高歩留まりで製造できるという効果
を有する。
[Effects of the Invention] As described above, according to the present invention, it is difficult to selectively etch pre-designed areas on an easily etched aluminum-silicon alloy formed entirely on a silicon oxide film. By forming a copper layer and removing the aluminum-silicon alloy by etching using the copper as a mask, it is possible to easily obtain a multilayer interconnection structure containing copper, which is difficult to remove by etching. It is possible to easily form a wiring having a lower resistance and a migration resistance of 8 ffl than that of the wiring, and has the effect that a highly reliable semiconductor device can be manufactured at a high yield.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の半導体装置の製造方法により得られ
る半導体装置の構造を示す断面図。 第2図(a)〜(e)は、本発明の半導体装置の製造方
法の実施例を示す工程断面図。 第3図は、従来の半導体装置の構造の実施例を示す断面
図。 103.303  アルミニウムーシリコン合金104
      フォトレジスト 105銅 風上 出願人 セイコーエプソン株式会社 代理人 弁理土鈴木喜三部他1名 101.301  半導体基板 102.302   酸化珪素膜 3oa
FIG. 1 is a cross-sectional view showing the structure of a semiconductor device obtained by the method of manufacturing a semiconductor device of the present invention. FIGS. 2(a) to 2(e) are process cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device of the present invention. FIG. 3 is a cross-sectional view showing an example of the structure of a conventional semiconductor device. 103.303 Aluminum-silicon alloy 104
Photoresist 105 Copper Windward Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Kizobe Suzuki and 1 other person 101.301 Semiconductor substrate 102.302 Silicon oxide film 3 oa

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上方に形成された第一の絶縁膜上の全面に第
一の導電膜を形成する工程、前記第一の導電膜上の予め
設計された領域に第二の絶縁膜を形成する工程、前記第
一の導電膜上の前記第二の絶縁膜におおわれていない領
域に第二の導電膜を選択的に形成する工程、前記第二の
絶縁膜を除去する工程、前記第二の導電膜をマスクとし
て前記第一の導電膜を選択的に除去する工程より成るこ
とを特徴とする半導体装置の製造方法。
a step of forming a first conductive film on the entire surface of the first insulating film formed above the semiconductor substrate; a step of forming a second insulating film in a predesigned region on the first conductive film; a step of selectively forming a second conductive film on a region not covered with the second insulating film on the first conductive film; a step of removing the second insulating film; and a step of removing the second conductive film. A method for manufacturing a semiconductor device, comprising the step of selectively removing the first conductive film using as a mask.
JP9561989A 1989-04-14 1989-04-14 Manufacturing method of semiconductor device Pending JPH02272736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9561989A JPH02272736A (en) 1989-04-14 1989-04-14 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9561989A JPH02272736A (en) 1989-04-14 1989-04-14 Manufacturing method of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02272736A true JPH02272736A (en) 1990-11-07

Family

ID=14142562

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9561989A Pending JPH02272736A (en) 1989-04-14 1989-04-14 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02272736A (en)

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