JPH02274012A - Duty control circuit - Google Patents

Abstract

PURPOSE:To secure the correct duty by using a result of comparison of a voltage with a capacitor voltage (reference voltage) which is charged only in a period in which a ramp wave, and detection current of an electric conduction current (output current) of a transistor exceed a set current value, and discharging in other period. CONSTITUTION:A reference voltage is a voltage which is driven by an output of an inverter and detects an electric conduction current (output current) of a transistor, charged only in a period (S2 period) in which its detection current exceeds a set current value, and discharge in other period. In such a state, when the potential of the capacitor is below the potential V1, the capacitor is charged quickly up to this potential, and when it exceeds V1, the capacitor is brought to ramp wave charge by an inclination determined in advance. Also, when a ramp wave reaches V3, the capacitor is discharged quickly to the potential V2, and from this potential, the ramp wave sets an operation for discharging until a logical level of an input signal comes to '1' by an inclination determined in advance to one period. In such a way, the correct duty is secured extending over the whole area of the frequency of the input signal.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a duty control circuit for electrical signals, and in particular to an output transistor for a solenoid driver, etc. using an output signal in which the pulse width of an input signal is controlled to be reduced. It is used for drivers that turn on and off.

(Prior Art) This type of conventional technology uses a ramp wave synchronized with an input signal and a reference signal (F) to generate an output signal as shown in FIG.
/V signal (signal in which frequency is exchanged to voltage).

(Problem to be Solved by the Invention) However, in the above-mentioned conventional technology, if there is a fluctuation or sudden change in the input frequency F that determines the reference voltage level, the base voltage level becomes undefined, and the output signal may not be obtained or the There was a problem that the signal width became unstable.

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned problems and provide an excellent duty control circuit.

[Structure of the invention]

(Means and effects for solving the problems) The present invention provides: (1) means for obtaining an output signal having a predetermined duty as a result of calculation from a pulse signal input from the outside;
A capacitor voltage that detects a ramp wave synchronized with an input signal and the current flow (output current) of a transistor driven by the output signal, and is charged only during the period when the detected current exceeds the set current value, and discharged during other periods. (a reference voltage), the ramp wave is generated when the input signal rises from the first logic level to the second logic level or after a predetermined time delay from this rise. If is less than or equal to the set potential, it is rapidly charged to this potential, and if the potential is greater than the set potential, it is charged from that potential to a first potential at a predetermined slope, and when this potential is reached, it is charged to the first intermediate potential. The duty control circuit is characterized in that the duty control circuit is obtained from a circuit in which one cycle is an operation of rapidly discharging the voltage to a predetermined slope and discharging at a predetermined slope from this first intermediate potential until the logic level of the next input signal changes. . Further, the present invention provides: (2) changing the potential slope when the ramp wave discharges from the first intermediate potential, and when the input signal is at the first logic level and when the input signal is at the second logic level; The duty control circuit according to item (1) above, further comprising means. Further, the present invention is characterized in that (3) the above-mentioned (1) is characterized by comprising means for changing the slope of the ramp wave during discharge by changing the slope of the ramp wave according to the power supply voltage only when the human input signal is at a second logic level. ) is the duty control circuit described in section 2.

The present invention also comprises: (4) means for changing the potential slope of the reference voltage capacitor when it is discharged between when the input signal is at a first logic level and when the input signal is at a second logic level. The duty control circuit according to item (1) above is characterized in that:

Further, the present invention provides the following features: (5) The ramp wave and the reference voltage are compared only during the rising and slope period of the ramp wave, and the period during which the potential of the ramp wave is lower than the reference voltage is the period when the potential of the ramp wave is lower than the reference voltage. The duty control circuit according to item (1), further comprising means for converting a signal of a period obtained by subtracting from the first logic level period into a duty-controlled output signal. In addition, the present invention provides that (6) the potential of the ramp wave is within the width of the output signal;
The duty control circuit according to item (5), further comprising a means for determining that the width of the input signal is excessive and outputting no signal unconditionally if the width of the input signal falls below the intermediate potential of . Further, the present invention provides: (7) When the potential of the ramp wave decreases to a third intermediate potential that is equal to or greater than the second intermediate potential, duty control is prohibited and the input signal is output as an output signal. The duty control circuit according to item (6) above, further comprising means. In addition, the present invention provides: (8) When the potential of the ramp wave drops below the third intermediate potential, the capacitor voltage that creates the reference voltage is forcibly discharged, and the ramp wave voltage becomes higher than the reference voltage. (7) above, characterized by comprising means for prohibiting the duty control by making it so that
This is the duty control circuit described in . In addition, the present invention provides (9) the operation of charging and discharging the capacitor using an up/down counter.
) is the duty control circuit according to any one of the following items. Further, the present invention provides (10) any one of (1) to (9) above, characterized in that the voltage comparison is performed by a digital comparator.
This is the duty control circuit described in Section 1.

That is, in the present invention, the human input signal width is divided into t] and tl with the intersection of the ramp wave and the first potential as the border, and the 1° period (charging period of the rising slope of the ramp wave) is divided between the ramp wave and the reference voltage. is a period in which duty control can be performed by comparing t1, and tl is a period in which the output signal is always on, regardless of the relationship between the ramp wave and the reference voltage.In the period t1, the potential of the ramp wave is equal to the reference voltage. If the period below the potential is 1 degree, that is, the actual duty control period, and the period above the potential is tl, then input signal width + ti - mtl + t2 ... [1]
Control is performed to maintain the relationship between By selecting the rising slope of the ramp wave, duty control is performed in which the period t1 can be arbitrarily changed.

(Example) The present invention will be described in detail below with reference to the drawings. FIG. 1 is a circuit diagram of the same embodiment, and FIG. 2 is a timing chart explaining the operation of the same embodiment.

In the figure, 11 is a power supply terminal, 12 is a power supply section, 13 is a supply terminal for an input signal to be subjected to duty control, 14 is an inverter that derives an output signal subjected to duty control, 15 is a reference voltage capacitor, and 16 is a lamp voltage capacitor for,
17 is a potential Vo-V3 forming section. V3 is the first potential, and V2 r ”O+V are the first, second, and third potentials, respectively.
is the intermediate potential of 18 is a comparator that compares the potential v3 and the ramp wave. This comparison is based on transistor Q
169. This will be done in Q170. One is a ramp waveforming section. Here, when the fourth level of charging of the capacitor 16 reaches V3, the transistor Q218 stops charging, and the transistor Q215 reduces the ramp wave voltage to ■2. R
x is for ramp wave discharge. Reference numeral 20 denotes a reference voltage forming section for comparison with the ramp wave, which has a reference voltage charging section 21 and a reference voltage discharging section 22. Reference numeral 23 denotes a forming unit for a signal S1 that determines the duty control range t1.

The signal Sl from here is at the "12 level" only during the period tl. 24 is a supply unit for maximum output current information S2. 25
are an output signal forming section and a duty control inhibiting section. Here, an output signal is generated by comparing the reference voltage applied to the transistor Q137 and the ramp wave applied to the transistor Q140 (only during the S+-“1” period). The vo detection unit 26 compares the ramp wave with the potential Vo, and determines that the ramp wave is V. When the value falls below that level, a duty control prohibition signal is generated and this signal is sent to the duty control prohibition section 25. This means that the input signal “0”
This means that the period is long, and duty control is not necessary in this case, so duty control is prohibited.

An example of the operation of the above configuration is as shown in FIG. 2, in which ramp wave charging is started at the rising edge of the input signal.

The reference voltage is charged by detecting the current flowing current (output current) of the transistor driven by the output of the inverter 14, and only during the period (32 periods) in which the detected current exceeds the set current value.
In other periods, the voltage is discharged by the capacitor 16. If the potential of the capacitor 16 is below the potential vl,
The capacitor 16 is quickly charged to this potential, and if it exceeds vl, it is charged with a ramp wave from that potential at a predetermined slope, and when the ramp wave reaches V3, it is rapidly discharged to the potential V2, and from this potential, the capacitor 16 is ramped up. The wave has a predetermined slope, and one cycle is an operation of discharging until the logic level of the input signal becomes "1".

Here, considering the excessive duty (excessive width of the input signal "1"), the slope when the charge of the capacitor is discharged from v2 is calculated between when the input signal is "1" and when the input signal is "0". The operation of changing the voltage with time is performed at transistor Q210. Further, the slope of the ramp wave during discharge is changed by the power supply voltage only when the input signal is "1", and is separated into a slope when the power supply voltage is high and a slope when the power supply voltage is low. Further, the slope of the reference voltage capacitor 15 is changed between when the human input signal is "L" and when it is "O". For example, the reference voltage is always discharged except when the output current is maximum, and in order to make this a function of the input signal "1", switch SW2
I am trying to switch it with .

Also, as explained in equation [1] above, the duty control period is 1. in FIG. It is carried out during the period when the potential of the ramp wave is lower than the reference voltage in the time period tl, that is, the period tl,
This is achieved by controlling the duty control period of tl, but for this purpose the rising inclination angle of the ramp wave is selected.

In addition, in Figure 2, if the potential of the ramp wave becomes less than Vo during the period when the output signal is "1", it is determined that the duty is excessive (the width of the input signal is excessive) and the output is unconditionally output. The signal can also be set to "0".

On the other hand, the potential of the ramp wave is V in FIG. If it falls below, the vo detection unit 26 detects it.

Since this corresponds to a long "0" period of the input signal, duty control is not necessary in this case, and this control is prohibited by the prohibition section 25, so that the input signal is controlled as an output signal as it is. To achieve this control, when the ramp wave potential drops below the potential Vl, the reference voltage capacitor 1
The above duty control is prohibited by forcibly discharging the voltage 5 and making the ramp wave voltage higher than the reference voltage.

If the duty control is as described above, the time t in FIG.
2 can be secured, an appropriate duty can be secured over the entire input frequency range as shown in FIG. 3(a). In other words, in the past, as shown in Figure 4, it was difficult to guarantee the position of the reference voltage due to fluctuations in the frequency F, and there were problems such as excessive duty at low frequencies and insufficient duty at high frequencies. There is no such thing. Further, in the present invention, since the time t1°tl shown in FIG. 2 is ensured, responsiveness is good when the input signal frequency is rapidly swept as shown in FIG. 3(b). Incidentally, in the conventional example shown in FIG. 4, when the input frequency F suddenly changes, the reference voltage fluctuates and the output duty drops as shown in FIG. 3(b), but this does not occur in the present invention. In addition, the potentials Vo and V2 in Figure 2 are constant, and the discharge slope of the ramp wave is also constant once determined, so the time from V2 to Vo is constant, and the duty excessive detection function is good as shown in Figure 3 (C). It is. Therefore, it is possible to prevent accidents such as the output current waveform shown in FIG. 2 becoming excessive and heating the output transistor.

Note that the present invention is not limited to the above-described embodiments, and can be applied in various ways. For example, in the present invention, "rising" and "
The meanings of "falling edge,""charging,discharging," etc. can be considered not only in the positive direction, but also in the negative direction.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to ensure an appropriate duty over the entire frequency range of the input signal, the response when rapidly sweeping the frequency of the input signal is good, and the duty excessive detection function is improved. It is possible to provide a duty detection circuit with the following functions.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a timing chart for explaining the operation of the circuit, Fig. 3 is a characteristic diagram showing the effects of the above embodiment, and Fig. 4 is a conventional circuit. 3 is a timing chart showing the operation of FIG. 11...Power supply, 13...Input signal supply end, 14...
・Output signal sending inverter, 15... Base voltage capacitor, ]6... Ramp wave forming capacitor, 17
... Each potential forming section, 18... V3 detection comparator, one... ramp wave forming section, 20... base voltage forming section, 23... S1 forming section, 24... S2 supply Part, 2
5... Output signal forming section and duty control inhibiting section, 2
6...Vo detection section. Applicant's agent Patent attorney Takehiko Suzue Input frequency time shown in Figure

Claims (10)

[Claims] (1) As a means for obtaining an output signal having a predetermined duty as a result of calculation from a pulse signal input from the outside,
A capacitor voltage that detects a ramp wave synchronized with an input signal and the current flow (output current) of a transistor driven by the output signal, and is charged only during the period when the detected current exceeds the set current value, and discharged during other periods. (a reference voltage), the ramp wave is generated when the input signal rises from the first logic level to the second logic level or after a predetermined time delay from this rise. If is less than or equal to the set potential, it is rapidly charged to this potential, and if the potential is greater than the set potential, it is charged from that potential to a first potential at a predetermined slope, and when this potential is reached, it is charged to the first intermediate potential. 1. A duty control circuit characterized in that the duty control circuit is obtained from a circuit in which one cycle is an operation of rapidly discharging up to the first intermediate potential and discharging at a predetermined slope from this first intermediate potential until the logic level of the next input signal changes. (2) comprising means for changing the potential slope when the ramp wave is discharged from the first intermediate potential depending on when the input signal is at the first logic level and when the input signal is at the second logic level; The duty control circuit according to claim 1, characterized in that: (3) The duty control according to claim 1, further comprising means for changing the slope of the discharge of the ramp wave according to the power supply voltage only when the input signal is at a second logic level. circuit. (4) A device for changing the potential slope of the reference voltage capacitor when it is discharged between when the input signal is at a first logic level and when the input signal is at a second logic level. 1. The duty control circuit according to 1. (5) The comparison between the ramp wave and the reference voltage is performed only during the rising slope period of the ramp wave, and the period during which the potential of the ramp wave is lower than the reference voltage is determined as the first logic level of the previous input signal. 2. The duty control circuit according to claim 1, further comprising means for converting a signal of the period obtained by subtracting the period from the period into a duty-controlled output signal. (6) The potential of the ramp wave is within the width of the output signal.
6. The duty control circuit according to claim 5, further comprising means for determining that the width of the input signal is excessive and unconditionally outputting no output signal when the width of the input signal falls below an intermediate potential. (7) Means is provided for inhibiting duty control and outputting the input signal as an output signal when the potential of the ramp wave decreases to a third intermediate potential that is the same as or greater than the second intermediate potential. The duty control circuit according to claim 6, characterized in that: (8) When the potential of the ramp wave drops below the third intermediate potential, the capacitor voltage that creates the reference voltage is forcibly discharged so that the ramp wave voltage becomes higher than the reference voltage. 8. The duty control circuit according to claim 7, further comprising means for prohibiting said duty control. (9) The duty control circuit according to any one of claims 1 to 8, wherein the operation of charging and discharging the capacitor is performed by an up/down counter. (10) The duty control circuit according to any one of claims 1 to 9, wherein the voltage comparison is performed by a digital comparator.