JPH02275369A - Sampling/holding circuit - Google Patents

Abstract

PURPOSE:To achieve a higher sampling accuracy at a low level of an analog signal by setting a sampling period of a sampling/holding circuit on the higher- order bit side of a serial digital data. CONSTITUTION:A first serial digital data S1 is supplied to a D/A converter 1 and when a latch signal S2 attains an H level at a time t5, the data S1 is loaded and converted into an analog signal S3 at a time t6 while the analog signal S3 is latched. The signal S3 is supplied to one of analog switches 3 through a buffer amplifier 2. When a sample signal S4 attains a high level as outputted from a sample signal control means 6 at three bits from the higher- order side of a second serial digital data S1 supplied at a time t7, the switch 3 is turned ON. Under such a condition, a capacitor 4 connected to the other end of the switch 3 is charged with an analog signal S3 supplied through the amplifier 2, thereby achieving a sampling accuracy at a low level of the analog signal.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a sample and hold circuit suitable for use in holding an analog signal output from a D/A converter for a certain period of time.

"Prior Art" A sample and hold circuit is used to hold an analog signal for a certain period of time. For example, it is used when it is necessary to hold serial digital data for a certain period of time after it is converted into an analog signal by a D/A converter.

FIG. 5 is a block diagram showing the configuration of the above-described conventional sample-and-hold circuit and its peripheral circuits. Also, the 6th
The figure is a waveform diagram for explaining the operation of the circuit.

In this figure, in the D/A converter I, when the latch signal S2 becomes high level at time t, the first serial digital data S1 is taken in, and at time t, the analog signal S
Converted to 3. This analog signal S3 is supplied to one end of the analog switch 3 via the buffer amplifier 2. Then, at a predetermined timing, that is, at time t3 on the lower bit side of the second serial digital data,
When the sample signal S4 becomes high level, the analog switch 3 is turned on. When the analog switch 3 is turned on, the voltage is supplied to the capacitor 4 connected to the other end of the analog switch 3, charging this capacitor. Then, when the sample signal S4 becomes low level at time t4, the voltage of the analog signal S3 at time t4 is held in the capacitor 4, and this charged voltage is output from the buffer amplifier.

"Problems to be Solved by the Invention" Incidentally, in the conventional circuit described above, the sample timing of the sample and hold circuit is set to the LSB (least significant bit) side of the serial digital data supplied to the D/A converter. . Therefore, when capturing the analog signal output from the D/A converter, the data on the LSB side of the serial digital data currently being supplied to the D/A converter is processed as digital noise through the buffer amplifier of the sample and hold circuit. to invade. Therefore, in this sample and hold circuit, the digital noise is sampled and held, resulting in poor sampling accuracy. In particular, since the LSB side of the serial digital data represents a minute voltage of the analog signal, this sample-and-hold circuit has a problem in that the sampling accuracy at low levels of the analog signal is extremely degraded.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a sample-and-hold circuit that can improve sampling accuracy at low levels of analog signals.

"Means for Solving the Problem" In order to solve such problems, the present invention converts serial digital data, which is sequentially supplied in units of a predetermined number of bits, into an analog signal every time one unit of data supply is completed. In a sample and hold circuit that samples and holds an output signal of a D/A converter to be converted, a first circuit whose input terminal is supplied with an output signal of the D/A converter;
a buffer amplifier, an analog switch having one end connected to the output end of the first buffer amplifier and becoming conductive when a sample signal is supplied; one end connected to the other end of the analog switch; a grounded capacitor, a second buffer amplifier whose input end is connected to a connection point between the analog switch and the capacitor, and the D
/A converter is supplied with the next unit of serial digital data, starts sampling from the upper bit of that bit, and controls the sample signal so that sampling ends at the timing when the lower bit becomes a predetermined bit. It is characterized by comprising a signal control means.

"Operation" Serial digital data sequentially supplied in units of a predetermined number of bits is converted into an analog signal by a D/A converter every time one unit of data supply is completed. The analog signal output from this D/A converter is supplied to one end of the analog switch via a first buffer amplifier. Then, when the next unit of serial digital data is supplied to the D/A converter, sampling starts from the upper bit of that bit, and the sampling signal ends when the predetermined bit becomes lower. The signal is supplied from the signal control means to the analog switch. During the sampling period of this sample signal, the capacitor is charged with the analog signal. Then, at the timing of the end of the sampling, the charged voltage of the capacitor is held and outputted via the second buffer amplifier.

"Embodiments" Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plot diagram showing the configuration of an embodiment of the present invention. In this figure, parts corresponding to the parts of the conventional example shown in FIG. 5 are given the same reference numerals and explanations are omitted.

In this figure, reference numeral 6 denotes sample signal control means, which controls the sample signal S4 supplied to the analog switch 3. This sample signal control means 6 is
The upper three bits of the next unit of data after the one unit of data converted into the analog signal S3 by the D/A converter 1,
A sample signal S4 is output which is at the noise level from the first bit to the predetermined lower bit, that is, the 11th bit.

Next, the operation of this embodiment with the above configuration will be explained. Here, FIG. 2 is a waveform diagram for explaining the operation of this embodiment, and FIGS. 3 and 4 are waveform diagrams for explaining the distortion of the final output voltage of the same embodiment.

First, first serial digital data S1 shown in FIG. 2(a) is supplied to the D/A converter it.

In this D/A converter 1, at time t, Deu-Sochi signal S2
When becomes high level, the first 7 real digital data S1 is taken in and converted to an analog signal S3 at time t, and this analog signal S3 is latched. This analog signal S3 is supplied to one end of the analog switch 3 via the Nozomi/Nofa amplifier 2. Then, at time t9 shown in FIG. 2(d), that is, at the third bit from the upper side of the currently supplied second serial digital data S1, the sample signal S4 output from the sample signal control means 6 becomes high level. Then analog switch 3
turns on. When the analog switch 3 is turned on, the analog signal S3 supplied via the buffer amplifier 2 is charged to the capacitor 4 connected to the other end of the analog switch 3. While the sample signal S4 is at a high level, that is, from time t to time t8 of the 11th bit from the upper side of the second serial digital data, the voltage of the analog signal S3 is charged in the capacitor 4. Then, when the sample signal S4 from the sample signal control means 6 becomes low level at the 11th bit of the second serial digital data S1, that is, at time t8, the voltage of the analog signal S3 at time t8 is held in the capacitor 4. An analog signal on which distortion caused by the lower bit/node data of the serial digital data S1 shown in FIGS. 3 and 4 is not superimposed is outputted via the XI/nofa amplifier 5.

In this way, the sample period of the sample signal S4 outputted from the sample signal control means 6 is set to 11 bits from the MSB side.
By doing this up to point (g), the analog signal output from the nog/nofa amplifier 5 will have only theoretical distortion. That is,
Digital noise caused by the lower bits of the serial digital data S1 is no longer superimposed on the output voltage of the sample and hold circuit.

[Effects of the Invention] As described above, the present invention has the advantage that sampling precision at low levels of analog signals can be improved by holding the samples on the more significant bit side.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
Figure 2 is a waveform diagram for explaining the operation of the same embodiment;
4 and 4 are waveform diagrams for explaining the distortion of the final output voltage of the same embodiment, FIG. 5 is a block diagram showing the configuration of the conventional sample-and-hold circuit and peripheral circuits, and FIG. 6 is the operation of the conventional example. FIG. 2 is a waveform diagram for explaining. 1... D/A conversion] 2... Buffer amplifier (first buffer amplifier), 3... Analog switch, 4... Capacitor, 5... ...
...Buffer amplifier (second buffer amplifier), 6...
...Sample signal control means.

Claims (1)

[Claims] A sample and hold circuit that samples and holds the output signal of a D/A converter that converts serial digital data sequentially supplied in units of a predetermined number of bits into an analog signal every time one unit of data supply is completed. a first circuit whose input terminal is supplied with the output signal of the D/A converter;
a buffer amplifier, an analog switch having one end connected to the output end of the first buffer amplifier and becoming conductive when a sample signal is supplied; one end connected to the other end of the analog switch; a grounded capacitor, a second buffer amplifier whose input end is connected to a connection point between the analog switch and the capacitor, and the D
/A converter is supplied with the next unit of serial digital data, starts sampling from the upper bit of that bit, and controls the sample signal so that sampling ends at the timing when the lower bit becomes a predetermined bit. A sample and hold circuit comprising signal control means.