JPH02275413A - Manufacture of matrix type display device - Google Patents

Manufacture of matrix type display device

Info

Publication number
JPH02275413A
JPH02275413A JP1098145A JP9814589A JPH02275413A JP H02275413 A JPH02275413 A JP H02275413A JP 1098145 A JP1098145 A JP 1098145A JP 9814589 A JP9814589 A JP 9814589A JP H02275413 A JPH02275413 A JP H02275413A
Authority
JP
Japan
Prior art keywords
display device
wiring
array substrate
gate electrode
electrode wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1098145A
Other languages
Japanese (ja)
Inventor
Masayuki Yokomizo
政幸 横溝
Takashi Sugawara
隆 菅原
Naoki Nakagawa
直紀 中川
Shigeru Yanai
谷内 滋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1098145A priority Critical patent/JPH02275413A/en
Publication of JPH02275413A publication Critical patent/JPH02275413A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 [産業上の利用分野コ この発明はマトリクス型表示装置の製造方法、特に薄1
]111−ランジスタアレイ基板の製造方法に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] This invention relates to a method of manufacturing a matrix type display device, particularly a thin one
]111-Relates to a method of manufacturing a transistor array substrate.

[従来の技術] 従来のマトリクス型表示装置は、一般的に基板上に複数
のゲート電極配線と複数のソース電極配線とを交差させ
、各々のゲート電極配線とソース電極配線との交点にス
イッチング素子を設けて構成されている。第3図はこの
1例を示しており、図においてb1〜bフはゲート電極
配線、31〜a5はソース電極配線であり、c 1. 
c 2.・・・は各々の電極配線の交点に接続されたス
イッチング素子である。これを少なくとも一方の基板上
に構成し、透明電極を有する対向基板との間に液晶等の
表示り料を挟持させる二とにより、液晶表示装置を構成
している。
[Prior Art] A conventional matrix display device generally has a plurality of gate electrode wirings and a plurality of source electrode wirings intersecting on a substrate, and a switching element is installed at the intersection of each gate electrode wiring and source electrode wiring. It is configured with the following. FIG. 3 shows an example of this, in which b1 to b are gate electrode wirings, 31 to a5 are source electrode wirings, and c1.
c2. . . . is a switching element connected to the intersection of each electrode wiring. A liquid crystal display device is constructed by configuring this on at least one substrate and sandwiching a display material such as liquid crystal between the two substrates and a counter substrate having a transparent electrode.

スイッチング素子C1,C2,・・・として、少なくと
も1ケの;iJ膜トランジスタ(以下、TPTと略す)
等の非線形特性を有する能動素子を用いた場合、第3図
に示すように各電極配線が互いに独立しているため、T
PT及びTPTのドレイン電極に接続された透明表示電
極、及び上記配線からなるTFTアレイ基板は静電気に
よる絶縁破壊等を引き起こしやすい。
At least one iJ film transistor (hereinafter abbreviated as TPT) is used as the switching element C1, C2,...
When using an active element with nonlinear characteristics such as
A TFT array substrate consisting of transparent display electrodes connected to the drain electrodes of PT and TPT, and the above-mentioned wiring is likely to cause dielectric breakdown due to static electricity.

このため、従来においては静電気による素子破壊の対策
として、各電極配線間を短絡することによ11、各電極
配線を同電位に保ち、TFTアレイ基板が静電気にさら
されても影響を受けないような構造がとられていた。
For this reason, in the past, as a countermeasure against element destruction due to static electricity, each electrode wiring was kept at the same potential by short-circuiting between each electrode wiring11, so that even if the TFT array substrate was exposed to static electricity, it would not be affected. A structure was adopted.

第2図は例えば特開昭58−116573号公報に示さ
れた従来のゲート電極配線及びソース電極配線を短絡す
る方法を示すTFTアレイ基板の構成例を示したもので
ある。図において、a1〜a6はソース電極配線、bI
Nb5はゲート電極配線であって、Cl+ C2,・・
・は各電極配線の交差点に設けたスイッチング素子であ
る。ここで、ソースai配ma〜a6は全て端子部にお
いて、図中のA及びDのように短絡されており、またゲ
ート電極配線 b。
FIG. 2 shows an example of the structure of a TFT array substrate showing a conventional method of short-circuiting gate electrode wiring and source electrode wiring as disclosed in, for example, Japanese Patent Laid-Open No. 58-116573. In the figure, a1 to a6 are source electrode wiring, bI
Nb5 is the gate electrode wiring, and Cl+ C2,...
* is a switching element provided at the intersection of each electrode wiring. Here, the source ai wiring ma to a6 are all short-circuited at the terminal portions as shown in A and D in the figure, and the gate electrode wiring b.

〜b、は全での端子部において、図中のB及びCにより
短絡されている。さらに短絡された端子間は図中、波線
で示されたようにA−8間はE、  A−6間はF、B
−D間はH,C−D間はGでそれぞれ接続すると、すべ
ての電極配線は短絡状態になるので、TFTアレイ基板
が静電気にさらされても、TFTアレイ基板内はいたる
ところで同電位であるので、スイッチング素子C++C
2−・・・は静電気により破壊されることはない。
-b are short-circuited by B and C in the figure at all terminal portions. Furthermore, between the shorted terminals, as shown by the wavy lines in the diagram, E is connected between A and 8, F is connected between A and B, and B is connected between A and 6.
When connecting -D with H and C-D with G, all electrode wiring becomes short-circuited, so even if the TFT array substrate is exposed to static electricity, the potential inside the TFT array substrate is the same everywhere. Therefore, switching element C++C
2-... will not be destroyed by static electricity.

[発明が解決しようとする課題] 従来のマトリクス型表示装置では以上のような方法によ
り、基板のハンドリング等の比較的低電圧あるいは除電
しやすい工程における静電気に対してはスイッチング素
子等の保護効果があったが、液晶デイスプレィ組立て工
程中の、液晶配向膜をラビング布で表面をこする事によ
り液晶を配向可能にするラビング処理工程のように、時
として数千ボルト以上もの高電圧静電気が発生する工程
においては、短絡線が設置されている場合等においても
絶縁物であるラビング布と金属表面の露出している基板
配線端子等が近接するとき、相互間で高電圧で電圧持続
時間の短いパルスコロナ放電が発生しやすく、このよう
な放電サージが配線端子等に印加された場合、各電極配
線を短絡させる短絡配線を用いていても、表示用スイッ
チング素子の素子特性劣化や電極配線間短絡等の静電気
障害が発生しやすい等の問題があった。
[Problems to be Solved by the Invention] In the conventional matrix display device, the above-mentioned method is effective in protecting switching elements, etc. against static electricity during relatively low voltage or easy-to-remove processes such as handling of substrates. However, during the LCD assembly process, high-voltage static electricity of several thousand volts or more is sometimes generated, such as in the rubbing process that allows the liquid crystal to align by rubbing the surface of the liquid crystal alignment film with a rubbing cloth. In the process, even when short-circuit wires are installed, when the rubbing cloth, which is an insulating material, and the board wiring terminals with exposed metal surfaces are close to each other, high voltage and short voltage duration pulses are applied between them. Corona discharge is likely to occur, and if such a discharge surge is applied to wiring terminals, etc., even if short-circuit wiring is used to short-circuit each electrode wiring, it may cause deterioration of the element characteristics of the display switching element or short-circuit between electrode wiring, etc. There were problems such as the tendency for static electricity damage to occur.

この発明は上記のような問題点を解消するためになされ
たもので、ラビング処理工程においてパルスコロナ放電
や放電サージが配線端子等に印加され難いような構成に
することにより、表示画面内のスイッチング素子等の静
電気障害を回避することが出来るマトリクス型表示装置
の製造方法を1厚ることを目的とする。
This invention was made to solve the above-mentioned problems, and by making it difficult for pulse corona discharge or discharge surge to be applied to the wiring terminals etc. during the rubbing process, switching in the display screen can be improved. The purpose of this invention is to increase the thickness of a matrix type display device manufacturing method that can avoid electrostatic damage to elements and the like.

[課題を解決するための手段] この発明に係るマトリクス表示装置の製造方法は、TF
Tアレイ基板上のゲート電融配線及びソス電斯配線の各
端子部分上を、絶縁性の膜で覆ノてラビング処理を行な
うようにしたものである。
[Means for Solving the Problems] A method for manufacturing a matrix display device according to the present invention includes a method for manufacturing a matrix display device according to the present invention.
Each terminal portion of the gate electrical wiring and the SOS electrical wiring on the T-array substrate is covered with an insulating film and subjected to a rubbing process.

「作用」 この発明においては、マI・リクス配凍の金属部分を絶
縁性の膜で覆い、ラビング処理をすることにより、ラビ
ング布とTFTアレイ基板の摩擦により発生した静電気
の、マトリクス配線とラビング布間での放電を防止し、
スイッチング素子の劣化を防止する。
"Operation" In this invention, by covering the metal part of the matrix distribution with an insulating film and performing a rubbing treatment, the static electricity generated by the friction between the rubbing cloth and the TFT array substrate can be removed from the matrix wiring and rubbed. Prevents discharge between cloths,
Prevent deterioration of switching elements.

[実施例コ 以下、この発明の一実施例によるマトリクス型表示装置
の製造方法を図について説明する。
[Embodiment 1] Hereinafter, a method for manufacturing a matrix type display device according to an embodiment of the present invention will be explained with reference to the drawings.

第1図はこの発明の一実施例に係わるマI・リクス型表
示装置のTFTアレイ基板の構成例を示した図であり、
 a1〜a5はソース電極配線、b、〜b3はゲート電
極配線であって、CI、C2,I・・は各電極配線の交
差点に設けたTPT等のスイッチング素子、d 、、 
d 2.・・・は外部駆動回路との接続用端子、り1)
はガラス等の透明絶縁性基板、(2〉は液晶配向処理用
のラビング布、(3)は絶縁比の膜である1゜ 次にその製造方法について説明する。
FIG. 1 is a diagram showing an example of the configuration of a TFT array substrate of a matrix type display device according to an embodiment of the present invention.
a1 to a5 are source electrode wirings, b, to b3 are gate electrode wirings, CI, C2, I... are switching elements such as TPT provided at the intersections of each electrode wiring, d,...
d2. ... is a terminal for connection with an external drive circuit, ri1)
(2) is a transparent insulating substrate such as glass, (2) is a rubbing cloth for liquid crystal alignment treatment, and (3) is a film with an insulation ratio of 1°.Next, the manufacturing method thereof will be explained.

TFTアレイ基板は、ガラス等の透明絶縁性基板(1〉
上にまずCr等をスパッタ法等を用いて成模し、フォト
リソグラフィー法等を用いてゲート重重配線を形成する
。次に、ゲート絶縁膜として5i3Nn等をP−CVD
法等を用いて成膜し、ひきつづきa  S+等の半導体
膜を成膜しホトリソグラフィー法等を用いてゲート絶縁
膜および半導体層を所望の形状に形成する、次にAI等
をスパッタ法などを用いて成膜し、フ第1・リソグラフ
ィー法等を用いてソース電極配線及び、 ドレイン電極
が形成される。次に酸化インジウム・スズ(ITo)等
をスパッタ法等を用いて成膜し、フォトリソグラフィー
法等を用いて透明表示電極を形成する。そして最後に5
ixN4等をP−CVD法等を用いて成膜し、TFTア
レイ基板が製造される。
The TFT array substrate is a transparent insulating substrate such as glass (1)
First, Cr or the like is formed on the surface using a sputtering method or the like, and a gate heavy interconnection is formed using a photolithography method or the like. Next, as a gate insulating film, 5i3Nn etc. is deposited by P-CVD.
Subsequently, a semiconductor film such as a S+ is formed, and a gate insulating film and a semiconductor layer are formed into a desired shape using a photolithography method. A source electrode wiring and a drain electrode are formed using a first lithography method or the like. Next, a film of indium tin oxide (ITo) or the like is formed using a sputtering method or the like, and a transparent display electrode is formed using a photolithography method or the like. and finally 5
A TFT array substrate is manufactured by forming a film of ixN4 or the like using a P-CVD method or the like.

なお、このSi3N4の膜はゲート電極配線及びソース
電極配線の外部回路との接続用端子部分を除く基板全面
に基板保護膜として形成される。次に、上記のTFTア
レイ基板の表示領域全面にポリイミド等の液晶配向膜を
形成し、液晶を配向させる217)ラビング処理を施す
が、このラビング処理工程においてゲート電極配線及び
ソース電極配線の、外部回路との接続用端子部分を、絶
縁性の膜、例えばポリイミドテープ等で覆って、各電極
配線端子の金属表面の露出を無くして、ラビング処理ヲ
行なうことにより、ラビング処理時のラビング布と外部
回路との接続用端子間での、コロナ放電や高パルス電圧
の各電極配線への印加を低減することが可能となり、T
FTアレイ基板のスイッチング素子破壊や、ゲート・ソ
ース配線間短絡といった静電気障害が防止される。
Note that this Si3N4 film is formed as a substrate protective film over the entire surface of the substrate except for terminal portions of the gate electrode wiring and the source electrode wiring for connection to external circuits. Next, a liquid crystal alignment film such as polyimide is formed on the entire display area of the TFT array substrate, and a rubbing process (217) is performed to align the liquid crystal. By covering the terminals for connection with the circuit with an insulating film, such as polyimide tape, to eliminate the exposure of the metal surface of each electrode wiring terminal, and performing the rubbing process, the rubbing cloth and the outside during the rubbing process can be It is possible to reduce corona discharge and the application of high pulse voltage to each electrode wiring between the terminals for connection with the circuit, and T
Electrostatic failures such as destruction of switching elements on the FT array substrate and short circuits between gate and source wiring are prevented.

[発明の効果] 以上のように、この発明によれば、ゲート電極配線、及
びソース電極配線の、外部回路と接続する端子部分を、
絶縁性の膜で葭ってラビング処理を行なうようにしたの
で、簡単にTFTアレイ基板の静電気障害による歩留ま
りの大幅な低下を防止でき、製造ゴス1−低減効果及び
信頼性を高める効果がある。
[Effects of the Invention] As described above, according to the present invention, the terminal portions of the gate electrode wiring and the source electrode wiring that connect to the external circuit,
Since the rubbing process is performed by covering the TFT array substrate with an insulating film, it is possible to easily prevent a large drop in yield due to electrostatic damage to the TFT array substrate, and there is an effect of reducing manufacturing dirt and improving reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例に係わるT F Tアレイ
基板の構成を説明する説明図、並びに第2図及び第3図
は従来の71−リクス型表示装置を示す構成図である。 図において、(1)は透明絶縁性基板、(2)はラビン
グ布、〈3)は絶縁性の膜、 a1〜a、はソース電極
配線、b、〜b3はゲーI・電極配線、cl、c2・・
はスイッチング素子、d、、d2.・・・は外部回路と
の接続用端子である。 なお、図中、同一符号は同一または相当部分をネオ。
FIG. 1 is an explanatory diagram illustrating the configuration of a TFT array substrate according to an embodiment of the present invention, and FIGS. 2 and 3 are configuration diagrams showing a conventional 71-lix type display device. In the figure, (1) is a transparent insulating substrate, (2) is a rubbing cloth, <3) is an insulating film, a1 to a are source electrode wirings, b, to b3 are gate I electrode wirings, cl, c2...
are switching elements, d, d2. . . . is a terminal for connection with an external circuit. In addition, in the figures, the same reference numerals refer to the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims]  透明絶縁基板上に、複数のゲート電極配線、及びこれ
らゲート電極配線と交差する複数のソース電極配線を形
成し、上記ゲート電極配線と上記ソース電極配線との交
差点に非線形特性を有する能動素子を接続し、上記能動
素子のドレイン電極に透明電極を接続して構成された薄
膜トランジスタアレイ基板にラビング処理工程を施し、
この薄膜トランジスタアレイ基板と、透明電極が形成さ
れた対向基板との間に表示材料を介在させて製造される
マトリクス型表示装置において、上記ラビング処理行程
は、上記ゲート電極配線、及び上記ソース電極配線の、
外部回路と接続する端子部分を、絶縁性の膜で覆ってラ
ビング処理を行なうようにしたことを特徴とするマトリ
クス型表示装置の製造方法。
A plurality of gate electrode wirings and a plurality of source electrode wirings intersecting with these gate electrode wirings are formed on a transparent insulating substrate, and an active element having nonlinear characteristics is connected to the intersection of the gate electrode wirings and the source electrode wirings. Then, a rubbing process is performed on a thin film transistor array substrate configured by connecting a transparent electrode to the drain electrode of the active element,
In a matrix display device manufactured by interposing a display material between this thin film transistor array substrate and a counter substrate on which a transparent electrode is formed, the rubbing process is performed to remove the gate electrode wiring and the source electrode wiring. ,
1. A method for manufacturing a matrix display device, characterized in that a terminal portion connected to an external circuit is covered with an insulating film and subjected to a rubbing treatment.
JP1098145A 1989-04-17 1989-04-17 Manufacture of matrix type display device Pending JPH02275413A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1098145A JPH02275413A (en) 1989-04-17 1989-04-17 Manufacture of matrix type display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1098145A JPH02275413A (en) 1989-04-17 1989-04-17 Manufacture of matrix type display device

Publications (1)

Publication Number Publication Date
JPH02275413A true JPH02275413A (en) 1990-11-09

Family

ID=14212031

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1098145A Pending JPH02275413A (en) 1989-04-17 1989-04-17 Manufacture of matrix type display device

Country Status (1)

Country Link
JP (1) JPH02275413A (en)

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