JPH02275659A - Resin mold type semiconductor device - Google Patents

Resin mold type semiconductor device

Info

Publication number
JPH02275659A
JPH02275659A JP1097978A JP9797889A JPH02275659A JP H02275659 A JPH02275659 A JP H02275659A JP 1097978 A JP1097978 A JP 1097978A JP 9797889 A JP9797889 A JP 9797889A JP H02275659 A JPH02275659 A JP H02275659A
Authority
JP
Japan
Prior art keywords
lead frame
semiconductor device
lead
resin
molded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1097978A
Other languages
Japanese (ja)
Other versions
JP2871716B2 (en
Inventor
Shoji Hashizume
昭二 橋詰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1097978A priority Critical patent/JP2871716B2/en
Publication of JPH02275659A publication Critical patent/JPH02275659A/en
Application granted granted Critical
Publication of JP2871716B2 publication Critical patent/JP2871716B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To decrease the mandays of machining, and to obtain a semiconductor device at low cost by exposing the Cu surface of a lead frame blank as it is to the surface of an external leading-out lead. CONSTITUTION:A semiconductor element 4 is mounted and fixed onto a lead frame 1 composed of Cu or a Cu alloy, and the electrode of the semiconductor element 4 and an inner lead are connected through wire bonding, and resin- molded 6. An oxide on the surface of the lead frame 1 in a section not resin- molded is removed, and the surface of the lead frame 1 is washed and dried. The unnecessary section of the lead frame 1 is cut lastly, and an external leading-out lead 1a is molded in a specified necessary shape, thus completing a semiconductor device. Accordingly, the film of solder plating, etc., is not formed to the external leading-out lead, and the complicating of an assembling process and the increase of cost can be avoided as Cu or a Cu alloy as the blank of the lead frame is left as it is.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂モールド型半導体装置に関し、特に表面が
Cuを主体とする素材からなるリードフレームを使用し
た樹脂モールド型半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin molded semiconductor device, and more particularly to a resin molded semiconductor device using a lead frame whose surface is made of a material mainly composed of Cu.

〔従来の技術〕[Conventional technology]

従来、この種の樹脂モールド型半導体装置は、Cu又は
Cu合金からなるリードフレームを使用し、半導体素子
をへgペースト等を用いてリードフレームにマウントし
た後、へgペーストをキュア(一般に150℃、2時間
)し、半導体素子をリードフレームに固着する。
Conventionally, this type of resin molded semiconductor device uses a lead frame made of Cu or Cu alloy, and after mounting the semiconductor element on the lead frame using Heg paste, etc., the Heg paste is cured (generally at 150°C). , 2 hours), and the semiconductor element is fixed to the lead frame.

その後、半導体素子の電極とリードフレームの内部リー
ドとを、Auワイヤ等によりボンディング接続(一般に
150〜350℃)する、更に、この半導体素子を保護
し、且つ外部導出リードを固定するために、樹脂モール
ド(一般に150〜175℃)を行う。
After that, the electrodes of the semiconductor element and the internal leads of the lead frame are connected by bonding (generally at 150 to 350°C) using Au wires, etc. Furthermore, in order to protect the semiconductor element and fix the external leads, a resin is applied. Mold (generally at 150-175°C) is carried out.

こうして組立てられた半導体装置は、組立工程(Agペ
ーストキュア工程、ワイヤボンディング工程、樹脂モー
ルド工程)中の加熱により、外部導出リードは酸化され
ている。そのため、一般に外部に導出したリード部には
、電解半田めっき法又はデイツプ法によって半田めっき
を施し、半導体装置が取り付けられる外部装置との電気
的接続の際に用いられる半田等の濡れ性を改善した構造
を有している。
In the semiconductor device thus assembled, the external leads are oxidized by heating during the assembly process (Ag paste curing process, wire bonding process, resin molding process). For this reason, the leads exposed to the outside are generally solder-plated using electrolytic solder plating or dipping to improve the wettability of the solder used to electrically connect the semiconductor device to an external device. It has a structure.

そして、半田めっきを施した後、不要リードフレーム部
を切断加工し、外部導出リードを成形加工して半導体装
置は完成する。又、リードフレームはワイヤボンディン
グ性を良くするために、内部リードのワイヤ接続部に部
分Agめっきを施したものが一般に使用されている。
After applying solder plating, unnecessary lead frame parts are cut and external leads are formed to complete the semiconductor device. Further, in order to improve wire bonding properties, a lead frame in which the wire connection portion of the internal lead is partially plated with Ag is generally used.

〔発明が解決し7ようとする課題〕 上述した従来の樹脂モールド型半導体装置は、樹脂モー
ルド後、外装めっきを施すために組立工程が複雑となり
、コスト高となっていた。
[Problems to be Solved by the Invention] The above-described conventional resin-molded semiconductor device has a complicated assembly process because exterior plating is applied after resin molding, resulting in high costs.

更に、電解半田めっき法では、通常、半田めっき液及び
その前処理工程での処理液に強酸溶液が使用され、半導
体装置はその強酸溶液中に長時間浸漬(15〜30分)
される。
Furthermore, in the electrolytic solder plating method, a strong acid solution is usually used as the solder plating solution and the treatment solution in the pretreatment process, and the semiconductor device is immersed in the strong acid solution for a long time (15 to 30 minutes).
be done.

そのため、リードフレームとモールド樹脂との微小隙間
に強酸溶液が侵入し、樹脂モールド境界のリードフレー
ムに内部腐食が生じ易くなり、更に、侵入イオンの除去
が困難となって残留イオンによる半導体装置の使用条件
下における電解腐食が生じ易くなり、電気的オーブン不
良が発生するという欠点を有していた。
As a result, a strong acid solution enters into the minute gap between the lead frame and the mold resin, making it easy for internal corrosion to occur in the lead frame at the boundary of the resin mold.Furthermore, it becomes difficult to remove the invading ions, and the semiconductor device cannot be used due to residual ions. This method has the disadvantage that electrolytic corrosion tends to occur under these conditions, resulting in electrical oven failure.

又、デイツプ法による半田めっきでは、半田めっき時の
温度が高い(250〜280°C)ために、半田デイツ
プ時の熱ストレスにより、リードフレームとモールド樹
脂との界面の隙間が大きくなり、プレッシャークツカー
テストなどの結果、耐湿性が原因で電気的絶縁性の劣化
が生じ易いといった欠点を有していた。
In addition, in solder plating using the dip method, the temperature during solder plating is high (250 to 280°C), so the gap at the interface between the lead frame and mold resin becomes large due to thermal stress during solder dip, resulting in pressure cracks. As a result of car tests, etc., it was found that it had the disadvantage of being susceptible to deterioration of electrical insulation due to its moisture resistance.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、少なくとも表面がCuを主体とする素材から
なるリードフレームを使用した樹脂モールド型半導体装
置において、樹脂モールド後に切断成形された外部導出
リードの表面にリードフレーム素材のCu面がそのまま
露出している樹脂モールド型半導体装置である。
The present invention provides a resin-molded semiconductor device using a lead frame whose surface is made of a material mainly composed of Cu, in which the Cu surface of the lead frame material is exposed as it is on the surface of the external lead-out lead that is cut and molded after resin molding. This is a resin molded semiconductor device.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の第1の実施例を示す縦断面図である。FIG. 1 is a longitudinal sectional view showing a first embodiment of the present invention.

Cu又はCuを主成分とする素材からなるリードフレー
ム1は、ワイヤボンディング性を改善するための部分^
gめっき2を内部リードに有している。このリードフレ
ーム1上に^gペースト3を用いて半導体素子4をマウ
ントし、その後Agペースト3をキュア硬化させ、半導
体素子4を固着している。
The lead frame 1 made of Cu or a material containing Cu as a main component is a part for improving wire bonding properties.
G plating 2 is provided on the internal leads. A semiconductor element 4 is mounted on this lead frame 1 using ^g paste 3, and then the Ag paste 3 is cured and the semiconductor element 4 is fixed.

又、半導体素子4の電極部(図示せず)とリードフレー
ム1の内部リード上の部分^gめつき2とを、Auワイ
ヤ5でボンディングしている。更に、半導体素子4等を
保護するために、エポキシ樹脂等のモールド樹脂6で封
止している。外部導出リード1aは、樹脂モールド後必
要形状に切断、成形されている。なお、外部導出リード
laは、半田めっき等の被膜を施しておらず、リードフ
レームの素材を露出させている。
Further, the electrode portion (not shown) of the semiconductor element 4 and the plating portion 2 on the internal lead of the lead frame 1 are bonded with Au wire 5. Furthermore, in order to protect the semiconductor element 4 and the like, it is sealed with a molding resin 6 such as epoxy resin. The external lead 1a is molded with resin and then cut and molded into a required shape. Note that the external lead la is not coated with a coating such as solder plating, and the material of the lead frame is exposed.

次に、本発明の樹脂モールド型半導体装置の製造方法に
ついて説明する。まず、半導体素子をCu又はCu合金
からなるリードフレーム上にマウント固着した後、ワイ
ヤボンディングによって半導体素子の電極と内部リード
とを接続し、樹脂モールドを行う。
Next, a method for manufacturing a resin molded semiconductor device of the present invention will be explained. First, a semiconductor element is mounted and fixed on a lead frame made of Cu or a Cu alloy, and then electrodes of the semiconductor element and internal leads are connected by wire bonding, and resin molding is performed.

しかる後に、一つの方法として5〜I 5wt%の塩酸
又は硫酸溶液中に30〜60秒浸漬し、樹脂モールドさ
れていない部分のリードフレーム表面の酸化物を除去し
た後純水洗浄し、その後80〜100℃のエアー中で3
〜IO分間乾燥する。
After that, one method is to immerse the lead frame in a hydrochloric acid or sulfuric acid solution containing 5 to 5 wt% for 30 to 60 seconds to remove oxides on the surface of the lead frame that are not resin-molded, and then wash it with pure water. 3 in ~100℃ air
Dry for ~IO minutes.

又、別の方法としては、組立工程中で高温となる工程、
すなわち半導体素子マウント固着、ワイヤボンディング
、樹脂モールドの各工程で還元性雰囲気(例えばN2を
5〜10vo1%含むN2カス)を用いることにより、
リードフレーム表面の酸化を防止する方法でもよい。
Another method is to use a process in which the temperature is high during the assembly process,
That is, by using a reducing atmosphere (for example, N2 scum containing 5 to 10 vol% N2) in each process of semiconductor element mounting fixing, wire bonding, and resin molding,
A method of preventing oxidation of the lead frame surface may also be used.

こうして得られた半導体装置のリードフレームの不要部
分を最後に切断し、所定の必要形状に外部導出リードを
成形して半導体装置を完成する。
Finally, unnecessary portions of the lead frame of the semiconductor device thus obtained are cut off, and external leads are formed into a predetermined required shape to complete the semiconductor device.

第2図は本発明の第2の実施例を示す縦断面図である。FIG. 2 is a longitudinal sectional view showing a second embodiment of the invention.

リードフレーム7は、Fe又はFe−Ni合金などのF
e系合金9からなり、Cuめつきが施されている。又、
ワイヤボンディング性を改善するために、内部リードに
部分Agめっき2が設けである。
The lead frame 7 is made of F such as Fe or Fe-Ni alloy.
It is made of e-based alloy 9 and is plated with Cu. or,
In order to improve wire bonding properties, a partial Ag plating 2 is provided on the internal leads.

このリードフレーム7上に、Agペースト3にて半導体
素子4を固着し、半導体素子4と内部リードの部分Ag
めっき2とをAuワイヤ5にてボンディング接続し、更
にモールド樹脂6を用いて封止している。
A semiconductor element 4 is fixed on this lead frame 7 with Ag paste 3, and a portion of the semiconductor element 4 and internal leads is Ag.
The plating 2 is bonded to the plating 2 using an Au wire 5, and further sealed using a mold resin 6.

外部導出リード7aは、第1の実施例と同様必要形状に
切断成形され、半田めっき等の被膜は施さず、リードフ
レーム素材のCuめつき部を露出させている。
The external leads 7a are cut and formed into the required shape as in the first embodiment, and are not coated with solder plating or the like, and the Cu plating portion of the lead frame material is exposed.

なお、組立工程中で前述の還元性雰囲気を使わない場合
、Cuめつき8の厚さは0.4μm以上が好ましい。0
.4μm未満では、下地のFe又はFe系合金9が酸化
し、外部装置との接続に使用する半田の濡れ性を悪くす
ることがある。
In addition, when the above-mentioned reducing atmosphere is not used during the assembly process, the thickness of the Cu plating 8 is preferably 0.4 μm or more. 0
.. If the thickness is less than 4 μm, the underlying Fe or Fe-based alloy 9 may be oxidized, resulting in poor wettability of solder used for connection with external devices.

次に、第1表(次頁)に、従来の半導体装置と本発明に
よる半導体装置との、半田付は性及びプレッシャークツ
カーテスト(PCT)による電気特性劣化の割合を、同
一形状、同一条件下で比敦した結果を示す。
Next, Table 1 (next page) shows the rate of deterioration of electrical characteristics by soldering and pressure test (PCT) between the conventional semiconductor device and the semiconductor device according to the present invention in the same shape and under the same conditions. The comparative results are shown below.

第1表 半田付は性及びPCT後電気特性劣化比較結果第1表に
よれば、本発明の半導体装置は半田付は性では差はなく
、耐湿性では改善されていることがわかる。
Table 1 Comparison results of soldering properties and deterioration of electrical properties after PCT According to Table 1, it can be seen that the semiconductor devices of the present invention have no difference in soldering properties, but are improved in moisture resistance.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、外部導出リードに半田め
っき等の被膜を形成せず、リードフレームの素材である
Cu又はCu系合金のままか、あるいはFe又はFe−
Ni合金に施したCuめっきをそのまま露出させている
。従って、加工工数が低減でき、低コストの半導体装置
を提供できる。
As explained above, the present invention does not form a coating such as solder plating on the external leads, and uses Cu or Cu-based alloy, which is the material of the lead frame, or Fe or Fe-
The Cu plating applied to the Ni alloy is exposed as is. Therefore, the number of processing steps can be reduced, and a low-cost semiconductor device can be provided.

又、電解半田めっき処理のような長時間の酸浸漬や、半
田デイツプ処理のような高温処理が樹脂モールド後不要
となり、耐湿性に優れた半導体装置を提供できる。
In addition, long-time acid immersion such as electrolytic solder plating or high-temperature treatment such as solder dip treatment is not required after resin molding, making it possible to provide a semiconductor device with excellent moisture resistance.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例の縦断面図、第2図は本
発明の第2の実施例の縦断面図である。 1・・・リードフレーム、1a・・・外部導出リード、
3・・Agペースト、4・・・半導体素子、5・・・A
uワイヤ、6・・・モールド樹脂、7・・・リードフレ
ーム、7a・・・外部導出リード、8・・・Cuめつき
、9・・・Fe又はFe系合金。 率 1 訂
FIG. 1 is a longitudinal sectional view of a first embodiment of the invention, and FIG. 2 is a longitudinal sectional view of a second embodiment of the invention. 1... Lead frame, 1a... External lead-out lead,
3...Ag paste, 4...semiconductor element, 5...A
u wire, 6... mold resin, 7... lead frame, 7a... external lead-out lead, 8... Cu plating, 9... Fe or Fe-based alloy. rate 1 revision

Claims (1)

【特許請求の範囲】[Claims] 少なくとも表面がCuを主体とする素材からなるリード
フレームを使用した樹脂モールド型半導体装置において
、樹脂モールド後に切断成形された外部導出リードの表
面にリードフレーム素材のCu面がそのまま露出してい
ることを特徴とする樹脂モールド型半導体装置。
In a resin-molded semiconductor device using a lead frame whose surface is made of a material mainly composed of Cu, the Cu surface of the lead frame material is exposed as it is on the surface of the external leads that are cut and molded after resin molding. Characteristics of resin molded semiconductor devices.
JP1097978A 1989-04-17 1989-04-17 Method for manufacturing resin-molded semiconductor device Expired - Fee Related JP2871716B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1097978A JP2871716B2 (en) 1989-04-17 1989-04-17 Method for manufacturing resin-molded semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1097978A JP2871716B2 (en) 1989-04-17 1989-04-17 Method for manufacturing resin-molded semiconductor device

Publications (2)

Publication Number Publication Date
JPH02275659A true JPH02275659A (en) 1990-11-09
JP2871716B2 JP2871716B2 (en) 1999-03-17

Family

ID=14206751

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1097978A Expired - Fee Related JP2871716B2 (en) 1989-04-17 1989-04-17 Method for manufacturing resin-molded semiconductor device

Country Status (1)

Country Link
JP (1) JP2871716B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0846107A (en) * 1994-08-04 1996-02-16 Naramoto Rika Kogyo Kk Drying method for semiconductor lead frame

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS633444A (en) * 1986-06-24 1988-01-08 Furukawa Electric Co Ltd:The Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS633444A (en) * 1986-06-24 1988-01-08 Furukawa Electric Co Ltd:The Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0846107A (en) * 1994-08-04 1996-02-16 Naramoto Rika Kogyo Kk Drying method for semiconductor lead frame

Also Published As

Publication number Publication date
JP2871716B2 (en) 1999-03-17

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