JPH02275665A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory having a capacitor of large capacity and adapted for miniaturization by simultaneously providing an opening of a cell plate with an opening for directly connecting to a bit line. CONSTITUTION:An opening 15 from the other regions of impurity regions 6a, 7a to a signal input/output conductive layer 70 is formed at a second insulating film 17, and a second electrode layer of a signal holding passive element 80 is extended to the side face of the opening 15 of the film 17. Here, a cell plate 10 and an interlayer insulating film 17 for holding the plate 10 are simultaneously opened with openings 15. Thus, a forming margin between the plate 10 and a bit line 12 is not required, and hence the plate 10 can be extended to the vicinity of the line 12. Thus, the capacity of a capacitor can be increased, and a memory cell can be miniaturized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device and a method for manufacturing the same, and particularly to a semiconductor memory device with an increased cell plate area of a dynamic random access memory and a method for manufacturing the same. Regarding the method.

[Background Art] In recent years, the demand for semiconductor memory devices has been rapidly increasing due to the remarkable spread of information devices such as computers. Furthermore, in terms of functionality, it is required to have a large storage capacity and be capable of high-speed operation. Along with this, technological development regarding higher integration, high-speed response, and high reliability of semiconductor memory devices is progressing.

Among conductive memory devices, DRA~1 (DynamicRandom
Access Memory). in general,
DRAM is composed of a memory cell array, which has a storage capacity for storing a large amount of stored information, and peripheral circuits necessary for outputting information to the outside.

FIG. 6 is a cross-sectional view of a 2-bit memory cell of a conventional DRAM. As shown in FIG.
0 is one access I transistor (switching element) 70 and one capacitor (passive element for signal holding) 8
It is composed of 0 and 0. Memory cell 60 is surrounded by a field oxide film 2 formed on the surface of semiconductor substrate 1, and is insulated from adjacent memory cells.

The access transistor 7o is located between the impurity regions 6a and 7a formed on the surface of the semiconductor substrate 1 and the impurity regions 6b and 7b, and is formed in a part of the semiconductor substrate 1 that becomes a channel region and on the channel region. The gate oxide film 3 is made up of a thin gate oxide film 3 and a gate electrode 4 formed on the gate oxide film 3.

The capacitor 80 has a dielectric film layer 9 made of a dielectric layer 1 such as a nitride film or an oxide film between a storage node 8 as an upper electrode made of a conductive material such as polycrystalline silicon and a cell plate 1o as an upper electrode. The storage node 8 is formed by depositing one impurity region 6 that functions as a source/drain region of the access transistor 7o.
b, connected to 7b. A bit line 12 is provided on the capacitor 8o with an insulating film 11 interposed therebetween. An opening 15 is provided in the insulating film 11, and the bit line 12 is electrically connected to the other impurity regions 6a, 7a through the opening 15.

In the process of manufacturing DRA~1 shown in FIG.
When forming an opening in 1, a resist film patterned using photomask 4 is used as a mask. Then, after wet etching, dry etching is performed to form an opening 15 that extends over the inclined surface 5o.

Next, the operation of the memory cell shown in FIG. 6 will be explained. A voltage equal to or higher than the threshold voltage is applied to the gate electrode 4.

This makes the source/drain regions 6a, 7a conductive to the source/drain regions 6b to 7b. Information is written and read by storing the signal charge on the bit line 12 in the capacitor 80i, or by extracting the charge from the capacitor.

[Invention or problem to be solved]

Recently, DRAMs have become increasingly dense and highly integrated. Along with this, the area of a capacitor for storing charge is becoming smaller and smaller, making it difficult to obtain a sufficient capacity with soft error resistance. Therefore, in order to obtain a memory cell that does not malfunction, it is necessary to increase the area of the capacitor.

On the other hand, in the conventional DRAM shown in FIG. 6, a margin M of about 063 μm is required between the end of the cell plate 10 and the bit line 12 for processing reasons. This margin has been an obstacle to increasing the size of the capacitor, and has been a major hindrance to the miniaturization of DRAMs.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device having a large capacitance capacitor and suitable for miniaturization, and a method for manufacturing the same.

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes two impurity regions formed at intervals on the surface of a semiconductor substrate, and a second impurity region located between the two impurity regions on the surface of the semiconductor substrate. a switching element including a conductive film formed through a first insulating film; a first electrode layer connected to one of the impurity regions of the switching element; and a first electrode layer formed in contact with the first electrode layer. a second dielectric film formed in contact with the dielectric film, and a second dielectric film formed in contact with the dielectric film.
a second insulating film formed to cover the switching element and the passive signal holding element, and an impurity region extending over the second insulating film. A semiconductor memory device including a memory region formed by arranging a plurality of unit memory circuits each having a signal input/output conductive layer electrically connected to the other region of the semiconductor memory device, the second insulating film having a conductive layer for signal input/output electrically connected to the other region.
An opening is formed from the other region of the impurity region to the signal input/output conductive layer, and the second electrode layer of the signal holding passive element extends to the side surface of the opening of the second insulating film.

The method for manufacturing a semiconductor memory device according to the present invention includes the steps of forming an element isolation region in a predetermined region on the surface of a semiconductor substrate, and forming two switching devices including a gate insulating film and a gate electrode on the surface of the semiconductor substrate surrounded by the element isolation region. A step of forming elements at intervals, a step of forming an impurity region on the semiconductor substrate surface between two switching elements and between a switching element and an element isolation region, and a region from one of the two switching elements to the other. forming a first insulating film covering the switching element and the element isolation region; forming an opening by etching the first insulating film between the switching element and the element isolation region; forming a first electrode layer partially in contact with the first insulating film and extending over the first insulating film; forming a dielectric layer on the first electrode layer; A step of forming a second electrode layer on the insulating film, a step of forming a second insulating film on the second electrode layer, and a step of etching away the region between the two switching elements. forming an opening that penetrates the insulating film, the second electrode layer, and the first insulating film.

[Operation] In the present invention, since the cell plate and the interlayer insulating film sandwiching the cell plate are opened at the same time, a processing margin between the cell plate and the bit line is not required. Therefore, since the cell plate can be extended to the vicinity of the bit line, the capacitance of the capacitor can be increased and the memory cell can be miniaturized.

[Embodiment of the Invention] FIG. 1 is a sectional view of a DRAM according to a first embodiment of the invention. Referring to FIG. 1, a memory cell 60 includes one access transistor (switching element) 70 and one capacitor (passive element for signal holding) 80. The peripheral region of the memory cell 60 is surrounded by an isolation region 20 having a field shield isolation structure. Separation area 20
An electrostatic shielding electrode 22 is formed on the surface of the semiconductor substrate 1 located at , with an oxide film 21 interposed therebetween. The electrostatic shielding electrode 22 includes
A ground potential or a negative potential is applied to the surface of the semiconductor substrate. This prevents a channel from being formed between adjacent memory cells 60 and causing conduction.

Impurity regions 6 are formed in the surface region of the semiconductor substrate 1 at intervals.
a, 7a and impurity regions 6b, 7b are formed. Impurity regions 6a and 6b are relatively low concentration regions, and impurity regions 7a and 7b are relatively high concentration regions. In other words, these impurity regions are so-called LDD (Li
Ght ly Dopped Drain) structure and tail. impurity regions 6a, 7a and impurity region 6b,
Gate electrode 4a is formed on the surface of semiconductor substrate 1 located between gate electrode 7b and gate oxide film 3.

Gate electrode 4a + gate oxide film 3 and impurity regions 6a, 7a and 6b, 7b constitute access transistor 70.

A pad 30a is formed on impurity regions 6a and 7a,
Band 30b is formed on impurity regions 6b and 7b. A plug 18 made of, for example, tungsten and extending vertically is formed on the pad 30a. bad 3
A storage node 8 of the capacitor 80 is formed on the layer 0b.
extending along the sides and top of the Therefore, the surface area of the storage node 8 is larger than that of the conventional example shown in FIG. 6, and the capacitance of the capacitor is correspondingly larger. A dielectric film 9 is formed on the storage node 8 .
A cell plate 10 is formed thereon. Cell plate 1
0 extends to the vicinity of the plug 18 and is electrically isolated from the plug 18 via a sidewall 19 made of an insulating film.

Storage node 8. Dielectric film 9 and cell plate 10
constitutes the capacitor 80.

Insulating film 17 is formed on capacitor 80 .

A lead electrode 31 electrically connected to the plug 18 is formed on the insulating film 17 . Further, an oxide film 32 is formed on the insulating film 17, and a bit line 12 electrically connected to the extraction electrode 31 is formed on the oxide film 32. bit line 1
2 is connected to a vertically extending plug 18,
Since there is no inclined portion 50 unlike the conventional example shown in FIG.
Two adjacent memory cells can be spaced apart by a short distance. Therefore, the structure shown in FIG. 1 is suitable for high density and high integration.

FIGS. 28 to 2L are process cross-sectional views for explaining the method of manufacturing the DRAM shown in FIG. 1.

Next, the manufacturing method of the first embodiment of the present invention will be described with reference to FIGS. 2A to 2L.

Referring to FIG. 2A, the entire main surface side of, for example, P-type silicon substrate 1 is thermally oxidized to form oxide film 21. Referring to FIG. next,
A polycrystalline silicon film 22 doped with impurities is formed on the oxide film 21. Next, an oxide film 23 is formed on the polycrystalline silicon film 22 using the CVD method. Next, a photoresist film 24 is applied, and only a predetermined area is exposed.
The photoresist film 24 is developed to remain only in the element isolation region.

Next, referring to FIG. 2B, etching is performed using the photoresist film 24 as a mask, and the above-mentioned three steps are performed only in the isolation region.
Leaving the layer membranes 21, 22, 23.

Next, referring to FIG. 2C, an oxide film 25 is formed on the entire surface using the CVD method. Next, referring to FIG. 2D, anisotropic etching is performed to leave sidewalls 26 only on the sidewalls of the three-layer film. As a result, isolation regions 20 using switching elements are formed.

Next, referring to FIG. 2E, the oxide film 23 of the isolation region 20 is
An oxide film 3 is formed on the surface of the semiconductor substrate 1 surrounded by the isolation region 20 . Subsequently, a polysilicon film 41 doped with impurities is deposited by, for example, a CVD method, and a high melting point metal film 42 is deposited thereon by a sputtering method.
For example, an oxide film 51 is deposited by, for example, a CVD method.

Next, a photoresist film 27 is formed in a predetermined area using a photolithography method, and the oxide film 51 is formed using the photoresist film 27 as a mask. The high melting point metal film 42, polysilicon film 41 and oxide film 3 are etched. As a result, as shown in FIG. 2F, one access transistor 70
A pole 4a is formed at the gate of the cell, and a word line 4b of an adjacent memory cell is formed. Next, impurity ions are implanted into the surface of the semiconductor substrate 1 using the gate electrode 4a and the isolation region 20 as a mask. As a result, low concentration impurity regions 6a and 6b are formed.

Next, referring to FIG. 2G, an insulating film 52 such as an oxide film is deposited over the entire surface of the semiconductor substrate 1 by, for example, the CVD method. Next, referring to FIG. 2H, the insulating film on impurity regions 6a and 6b is removed by anisotropic etching. As a result, a side wall 5 of the insulating film is formed on the side wall of the gate electrode 4a.
is formed.

Next, a polycrystalline silicon film is formed over the entire surface. Next, the polycrystalline silicon film is patterned into a predetermined shape using photolithography and etching. Thereby, as shown in FIG. 2I, the pad 30a, which is electrically connected to the impurity region 6a and extends on the opposing sidewalls 5 of the two adjacent gate electrodes 4a, is electrically connected to the impurity region 6b. A pad 30b is formed which extends over the sidewall 5 and the isolation region 20. Next, high-concentration impurity ions such as As are implanted into the impurity regions 6a and 6b so as to partially overlap each other, and heat treatment (
For example, at 900° C. for 30 minutes), activation is performed.

As a result, the impurity region 6 which becomes the source/drain region
a, 7a and 6b, 7b are formed.

Next, referring to FIG. 2J, an insulating film 11 is formed over the entire substrate using the CVD method. Next, secondly, referring to the figure, an opening 16 is provided by patterning. At this time, pad 30b serves to prevent etching of impurity regions 6b, 7b, the sidewalls of gate electrode 4a, and the sidewalls of word line 4b. Next, polycrystalline silicon is formed over the entire substrate, and then patterned using photolithography and etching to form storage nodes 8.

Next, referring to FIG. 2L, the entire surface of storage node 8 is thermally oxidized to form dielectric film 9 made of an oxide film. Next, a cell plate 1 made of polycrystalline silicon is placed so as to cover the dielectric film 9 and the insulating film 11.
form o.

Next, an insulating film 17 is formed on the cell plate 10, and a resist film 13 is formed on the insulating film 17.

Next, using a photolithography method, a resist film]3
An opening 15 is formed to expose a part of the insulating film 17. Next, using the resist film 13 as a mask, the insulating film 17 located under the opening 15 is etched using an anisotropic etching method. Cell plate 10 and insulating film 11 are removed all at once.

At this time, the pad 30a serves to prevent the impurity regions 6a, 7a and the sidewall 5 of the gate electrode 4a from being etched. Next, an oxide film is formed on the entire substrate using the CVD method, and a sidewall 19 (FIG. 1) is formed by anisotropic etching to cover the end of the cell plate 10 exposed on the side surface of the opening 15. Form.

Thereafter, a plug 18 made of tungsten is selectively formed only on the pad 30a in the opening 15. Finally, a lead electrode 31 made of polysilicon is formed by buttering, and then an oxide film 32 is formed using the CVD method, and an opening is formed on the polysilicon lead electrode 31. A bit line 12 is formed.

In the case of the conventional example shown in FIG. 6, since the patterning of the cell plate 10 and the patterning of the insulating film 11 are separate processes, separate masks were required. In the example, an insulating film 17, a cell plate 10. Since the insulating film 11 is etched at the same time, only one mask is required to etch them.

The features of the embodiment described above are as follows.

(a) An electrostatic shielding electrode 22 is used as an element separation method. The electrostatic shielding electrode 22 is a normal MOS (Metal
Similar to the Oxide Sem1 conductor)h transistor, it is wrapped in an insulating film and a predetermined voltage is applied to it. This prevents a channel from being formed between adjacent impurity regions and causing conduction.

(b) Pads 30a, 30b are provided in contact with the impurity regions 6a, 6b, 7a, 7b and the sidewall 5 of the gate electrode 4a located on the sides of the impurity regions. The pads 30a and 30b prevent the sidewall from being etched when forming contact holes.

(c) The capacitor 80 has a large surface area so as to have a large capacitance.

(d) The cell plate 10 extends to the vicinity of the plug 18.

(e) A side wall 19 is provided on the side surface of the opening 15.
is formed to prevent short circuit between the tungsten plug 18 connected to the bit line 12 and the cell plate 10.

(f) Bit line 12 is electrically connected to impurity regions 6a and 7a via plug 18 extending vertically. Unlike the conventional example, since there is no inclined part of the bit line, two adjacent memory cells can be arranged at a short interval. From the above, it is possible to form miniaturized memory cells and provide a highly integrated DRAM.

FIG. 3 is a sectional view showing a DRAM according to a second embodiment of the invention. Referring to FIG. 3, storage node 8 extends from above gate electrode 4a to above word line 4b passing over impurity regions 6b and 7b and above electrostatic shielding electrode 22 in red. Furthermore, a part of it is a standing wall portion 81 extending in the vertical direction.
have.

In the vertical wall portion 81, both the inner wall portion 8a and the outer wall portion 8b are used as a capacitor. Therefore, the surface area of the storage node 8 increases dramatically. Gate electrode 4
A nitride film 91a is formed on the word line 4b, and a nitride film 91b is formed on the word line 4b. As will be explained later, the nitride films 91a and 91b serve to prevent the insulating film on the gate electrode and word line from being etched.

Next, the manufacturing process of the DRAM memory cell shown in FIG. 3 will be described with reference to FIGS. 4A to 4J.

Note that the steps before FIG. 4A are shown in FIGS. 2A to 2H.
Since the process is similar to the process shown in the figure, the explanation will be omitted.

Referring to FIG. 4A, after sidewalls 5 of gate electrode 4a are formed, high concentration impurity ions are implanted using sidewalls 5 as a mask.

As a result, high concentration impurity regions 7a and 7b are formed on the surface of the semiconductor substrate 1 between the gate electrodes 4a and between the gate electrodes 4a and the electrostatic shielding electrode 22. At the same time, L.D.D.
The structure is constructed. Next, a nitride film is formed on the entire surface of the semiconductor substrate 1 by a low pressure CVD method, and the nitride film is patterned into a predetermined shape using a photolithography method and an etching method. As a result, one gate electrode 4
A nitride film 91a extends from above the impurity regions 6a and 2a to the other gate 7 [S pole 4a], and a nitride film 9 extends above the word line 4b and the electrostatic shielding electrode 22.
1b is obtained.

Next, referring to FIG. 4B, a polycrystalline silicon layer is formed on the entire surface of the semiconductor substrate 1 using a low pressure CVD method, and the polycrystalline silicon layer is etched into a predetermined shape using a photolithography method and an etching method. Buttering into shape. Thereby, pad 30b connected to impurity regions 6b and 7b between gate electrode 4a and word line 4b is formed.

The pad 30b is shaped such that both ends thereof ride on the nitride films 91a and 91b.

Next, referring to FIG. 4C, a thick and flat insulating film 171 is formed on the upper surfaces of nitride films 91a, 91b and pad 30b using the CVD method.

The thickness of the insulating film 171 defines the height of the vertical wall portion 81 of the storage node 8 formed in a subsequent step. Next, a photoresist film is applied on the insulating film 171 and patterned into a predetermined shape, and the insulating film 171 is etched using the photoresist film 44 as a mask. This results in
An opening 16 is formed in the insulating film 171 on the pad 30b.

Next, referring to FIG. 4D, a polycrystalline silicon layer 45 is formed on the surface of the insulating film 171 and inside the opening 16 using a low pressure CVD method.

Next, referring to FIG. 4E, polycrystalline silicon layer 45 is selectively removed by anisotropic etching.

As a result, the polycrystalline silicon layer 45 formed on the flat surface of the insulating film 171 and the upper surface of the pad 30b is selectively removed, leaving the polycrystalline silicon layer 45 formed on the inner surface of the opening 16. .

Through this process, storage node 8 or barad 3
A vertical wall portion 81 of the storage node is formed which is integrated with 0b.

Next, using the nitride films 91a and 91b as masks, the insulating film 17 is
1 is completely removed. The state after removal is shown in FIG. 4F. The nitride films 91a and 91b protect the insulating film on the gate electrode 4a and word line 4b from being etched.

Next, impurities are implanted into the storage node 8 having the vertical wall portion 81 with oblique rotation.

Next, referring to FIG. 4G, a nitride film is formed on the entire surface using a low pressure CVD method, and then the semiconductor substrate 1 is heat-treated in an oxygen atmosphere to oxidize a part of the formed nitride film, A dielectric film 9 made of a composite film of a nitride film and an oxide film is formed. This dielectric film 9 is formed to completely cover the surface of the storage node 8 and extend over the nitride films 91a and 91b. Thereafter, a polycrystalline silicon layer 10 serving as a cellular 1 note is formed on the dielectric film 9 using a low pressure CVD method.

Next, a thick and flat interlayer insulating film 17 is formed on the polycrystalline silicon layer 10 by the CVD method.

Next, referring to FIG. 4H, a photoresist film 46 is formed on the interlayer insulating film 17. Next, etching is performed to form openings 15 in portions of resist film 46 located above impurity regions 6a and 7a, exposing a portion of the surface of interlayer insulating film 17.

Next, using the resist film 46 as a mask and using an anisotropic etching method, the insulating film 17 . Polycrystalline silicon layer 10. Dielectric film 9 and nitride film 91a are removed all at once.

Next, referring to FIG. 4I, an insulating film 47 is formed on the interlayer insulating film 17 and inside the opening 15 using the CVD method, and an insulating film 47 is formed on the interlayer insulating film 17 using an anisotropic etching method. The insulating film 47 is removed, leaving the sidewall 19 on the inner wall of the opening 15. Next, a plug 18 made of tungsten is formed in the opening 15 covered with the sidewall 19 so as to be connected to the impurity regions 6a and 7a. next,
A bit line 1 made of a conductive film is connected to the plug 18.
form 2. Through these steps, a DRAM memory cell having the structure shown in FIG. 3 is obtained.

FIG. 5 is a diagram showing a modification of the second embodiment.

In the DRAM shown in FIG. 5, unlike the one shown in FIG. 3, nitride films 91a and 91b are formed so as to ride on the pad 30b forming a part of the storage notebook 8. In this structure, the pad 3ob is covered with a nitride film 91. a, 9
], buttering before b, i.e. 4th A
This can be obtained by reversing the steps shown in the figure and the steps shown in FIG. 4B.

Note that in the above embodiment, a transistor was used to separate the gate oxide film and the electrostatic shielding electrode for element isolation, but this could also be LOGO3/Ai4'1E, or a trench could be formed to separate the oxide film. Buried trench isolation may also be used.

In addition, in the above embodiment, the LDD tM structure is used for the source and drain of the transistor, but it may be a single source and drain, and it can also be used as a DDD transistor, a gate overlap transistor, or any other type of transistor. It is also possible to use a type (&), which produces the same effect as the above-mentioned embodiment.

Further, in the above embodiments, an n-channel transistor is used, but a p-channel transistor may also be used. In this case, the substrate is an n-channel transistor.
A mold is used, and boron, for example, is used as an impurity for forming the source/drain regions.

[Effects of the Invention] As described above, according to the present invention, by providing the opening in the cell plate at the same time as the opening for direct connection to the bit line, no margin is required for overlapping and processing. The area of the capacitor can be made larger. Further, by reducing the number of masks by one, it is possible to simplify the process.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a DRAM according to a first embodiment of the present invention. Figures 2A to 2L are DR shown in Figure 1.
FIG. 3 is a process cross-sectional view for explaining the AM manufacturing method. FIG. 3 is a sectional view showing a DRAM according to a second embodiment of the invention. Figures 48 to 41 are the DRA shown in Figure 3.
It is a process sectional view showing the manufacturing method of M. FIG. 5 is a diagram showing a modification of the second embodiment. FIG. 6 is a sectional view of a conventional semiconductor memory device. In the figure, 1 is a semiconductor substrate, 3 is a gate insulating film, and 4a
is the gate electrode, 5 is the side wall, 6a+6b
+ 7 a + 7 b is an impurity region, 8 is a storage node, 9 is a dielectric film, 10 is a cell plate, 11 and 17 are insulating films, 12 is a bit line, 18 is a plug, 19
20 is a side wall, 20 is an isolation region, 22 is an electrostatic shielding electrode, 30a, 30b are pads, 60 is a memory cell, 70
indicates an access transistor, and 80 indicates a capacitor. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] (1) Two impurity regions formed at intervals on the surface of a semiconductor substrate, and a conductive film located between the two impurity regions and formed on the surface of the semiconductor substrate via a first insulating film. a switching element comprising: a first electrode layer connected to one of the impurity regions of the switching element; a dielectric film formed in contact with the first electrode layer; a second insulating film formed to cover the switching element and the passive signal holding element; and a second insulating film formed on the second insulating film. A semiconductor memory device including a memory region formed by arranging a plurality of unit memory circuits each having a conductive layer for signal input/output extending from the impurity region and electrically connected to the other region of the impurity region. An opening extending from the other region of the impurity region to the signal input/output conductive layer is formed in the insulating film, and the second electrode layer of the signal holding passive element is formed in the second insulating film. A semiconductor memory device characterized by extending to a side surface of an opening. (2) forming an element isolation region in a predetermined region on the surface of the semiconductor substrate; and forming two switching elements including a gate insulating film and a gate electrode on the surface of the semiconductor substrate surrounded by the element isolation region; forming an impurity region on the surface of the semiconductor substrate between the two switching elements and between the switching element and the element isolation region; forming a first insulating film to cover the switching element; forming an opening in the first insulating film between the switching element and the element isolation region; forming a first electrode layer partially in contact with the first insulating film and extending over the first insulating film; forming a dielectric layer on the first electrode layer; and the dielectric layer and forming a second electrode layer on the first insulating film; forming a second insulating film on the second electrode layer; and etching away a region between the two switching elements. A method of manufacturing a semiconductor memory device, comprising: forming an opening that penetrates the second insulating film, the second electrode layer, and the first insulating film.