JPH02276251A - Semiconductor device - Google Patents

Abstract

PURPOSE:To restrain the deterioration of hot carriers including the initial deterioration of the carriers as well by a method wherein sidewalls are formed of a conductor layer on the sidewalls of each gate elect rode being insulated from the gate electrode and these sidewalls are connected with a drain in such a way that they are set at a potential identical with that of the drain. CONSTITUTION:Sidewalls 26, which are arranged on each gate oxide film 23 and are extendedly provided on a field oxide film 22, are formed on the sidewalls of each gate electrode 24 being insulated from the gate electrode 24 by each insulating film 25. These sidewalls 26 are formed of a conductor layer consisting of an impurity-doped polycrystalline silicon layer or the like. Moreover, on both sides of a gate structure part having these sidewalls 26 and the gate electrodes 24, n<+> source diffused regions 27 and an n<+> drain diffused region 28 are formed in a substrate 21. The sidewalls 26 are electrically connected to the region 28 through a connecting layer 29 consisting of an impurity-doped polycrystalline silicon layer or the like. Moreover, an Al wiring 30 is connected to the region 28.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and more particularly to a MOS PET having hot carrier resistance.

(Prior Art) Conventionally, as a structure of MOS PET having hot carrier resistance, L D
D (Lightly Doped Drain) structures have been used. FIG. 9 shows the cross-sectional structure of an N-channel ll0sP[iT having this structure. In this figure, 1 is a p-type silicon substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a gate electrode, and 5 is a side wall,
6 is a source diffusion region, 7 is a drain diffusion region, 8 is an n-
9 is an interlayer insulating film, 1o is an M wiring, and 11 is a pansivation film.

The feature of this structure is that in addition to the usual source diffusion region 6 and drain diffusion region 7, a low concentration (10''to''/cii
) exists. Since the electric field is relaxed by this n- region 8, the amount of hot carriers generated is reduced and deterioration of transistor characteristics is suppressed.

The manufacturing process of this LDD structure MOS FET is shown in FIG. 10. First, as shown in FIG. A doped polysilicon film 4' is formed, and a resist pattern 12 for gate patterning is formed on this polysilicon film 4'. Next, using this resist pattern 12 as a mask, the polysilicon film 4' is
The gate electrode 4 is patterned as shown in Figure 0 (b).
0 to form and further pattern the gate oxide film 3.
Next, phosphorus is ion-implanted into the substrate 1 using the gate electrode 4 as a mask to form an n- region 8 in the substrate 1. after that,
10th by CVD oxide deposition and anisotropic etching.
As shown in Figure (c), the sidewall 5 is connected to the gate electrode 4.
Formed on the side wall of. Then, by implanting arsenic ions using the sidewall 5 and gate electrode 4 as a mask, the source and the substrate 1 are implanted as shown in Fig. 1θ (d).
A drain diffusion region 6.7 is formed, and then heat treatment for activation is performed.

After that, as shown in FIG. 1(e), a glabellar insulating film 9 is deposited by a normal process, and a contact hole is opened.
M interconnection 10 is formed by M vapor deposition and patterning, and finally passivation film 11 is deposited.

(Problem to be solved by the invention) However, in the LDD structure as described above, n-61
Since the electric field spreads over the entire region 8, the electric field shape near the drain (drain diffusion region 7) is not delta function-like, and the peak intensity is small, but it becomes a shape with width and is quite strong even outside the gate electrode 4. An electric field distribution is formed. Therefore, the oxide film sidewall 5 which is not under the gate electrode 4
Hot carriers are also generated in the lower -zl region 8 due to impact ionization, and electrons are injected into and captured by the sidewall 5, pinching off the n- region 8. There is a problem in that this electron trapping process in the sidewall 5 causes initial deterioration due to hot carriers peculiar to LDDs.

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device that can suppress hot carrier deterioration, including the above-mentioned initial deterioration, and has extremely excellent hot carrier resistance.

(Means for Solving the Problems) This invention provides a MOS FET in which a sidewall is formed on the sidewall of a gate electrode with a conductor insulated from the sidewall,
This sidewall is connected to the drain (drain diffusion region) so that it has the same potential.

(Function) A typical method for suppressing hot carrier deterioration is to suppress the amount of hot carriers generated by relaxing the electric field near the drain, and the 1103 FET with the LDD structure is one of them. It is known that the amount of hot carriers generated strongly depends on the gate voltage as well as the impurity concentration. FIG. 11 shows the gate voltage dependence of substrate current and transfer conductance deterioration using drain voltage as a parameter.

Since the substrate current corresponds to the amount of hot carriers generated, the substrate current and transfer conductance degradation show almost the same dependence on the gate voltage and drain voltage. However, when the gate voltage is high, the substrate current and transfer conductance deteriorate It can be seen that conductance deterioration is significantly reduced. this is,
This is because the higher the gate voltage, the more relaxed the electric field near the drain becomes, making it difficult for hot carriers to be generated. However, in reality, the MOS FET operates by applying a pulse voltage to the gate electrode, so it is inevitable that there will be a state where the gate voltage is low.

Therefore, in the present invention, the sidewall is formed of a conductor and connected to the drain. In other words, the sidewall is used as another gate electrode and is always kept at a high potential that is the same as the drain. As a result, the amount of hot carriers generated is reduced by preventing a low gate voltage from occurring near the drain. This suppresses the deterioration of the host carrier.

Furthermore, although the present invention basically does not require an LDD structure, even with an LDD structure, if the sidewall is a conductor, initial deterioration as seen in a normal LDD structure MO5FET does not occur.

(Actual hIi example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a perspective view showing an embodiment of the present invention, in which two identical MOS FETs are formed on the same substrate. In this figure, 21 is a p-type silicon substrate, on which a field oxide film 22 is selectively formed. Further, a gate oxide film 23 is formed on the surface of the p-type silicon substrate 21, and a gate electrode 24 is formed thereon extending over the field oxide film 22. This gate electrode 24 is covered with an insulating film 25 on its top and side surfaces. A sidewall 26 is formed on the sidewall of the gate electrode 24 while being insulated by the insulating film 25, and is placed on the gate oxide film 23 and extends over the field oxide film 22. This sidewall 26 is formed of a conductor such as impurity-doped polysilicon. Further, n' source diffusion regions 27 and drain diffusion regions 28 are formed in the substrate 21 on both sides of the gate structure having the sidewalls 26 and the gate electrodes 24. A connection layer 29 made of impurity-doped polysilicon or the like is provided in the drain diffusion region 28.
The sidewalls 26 are electrically connected. Further, an M wiring 30 is connected to the drain diffusion region 28 .

In this MOS FET, a sidewall 26 made of a conductor is connected to a drain diffusion region 2B by a connection layer 29.
Since the side wall 2 is electrically connected to
6 is always kept at a high voltage that is the same potential as the drain diffusion region 28 (drain).

FIG. 2 is an equivalent circuit of the above MO5PET. In the equivalent circuit, three MOSFETs 41. 42. 43 are connected in series, and the MOS FE on both sides
The gate voltage of T41.43 is always equal to the drain voltage and is in the on state. Therefore, the central? IO3F
The gate voltage of ET 42 alone operates the entire transistor.

FIG. 3 is a pattern plan view of the above 1'lO5PET,
In particular, in FIG. 3, which shows the method of arranging the connection layer between the sidewall and the drain diffusion region, four portions A to D separated by broken lines each correspond to one transistor. The gate electrode 24 is surrounded by an insulating film 25 on all of its upper and side surfaces, and is electrically insulated from the sidewalls 26. The sidewall 26 is in contact with a connection layer 29 on the field oxide film 22, and the connection layer 29 is also in contact with a portion of the drain diffusion region 28. Further, the connection layer 29 and the gate electrode 24 are separated by the insulating film 25. 31 is a source wiring.

The MOS FET of one embodiment of this invention as described above is as follows:
It can be manufactured by making full use of ordinary semiconductor manufacturing technology and self-alignment technology, for example, according to the steps shown in FIGS. 4 to 8. In addition, in these figures, (a
) is a pattern plan view showing only the portions related to each process, (b) is a cross-sectional view taken along the line X--X, and (c) is a cross-sectional view taken along the Y-Y line.

■ Gate oxide film forming process (Fig. 4) After forming a field oxide film 22 with a thickness of 3000 to 500 nm on a p-type silicon substrate 21, gate oxidation is performed to form a gate oxide film 23a with a thickness of 100 to 500 nm. .

■ Gate electrode formation process (Fig. 5) The above field oxide film 22 and gate oxide film 23a
After depositing polysilicon to a thickness of 2,000 to 5,000 layers, phosphorus is diffused into the polysilicon layer. Next, on the polysilicon layer, 1,000~
The insulating film 25a is deposited to a thickness of 3,000 yen, and then the insulating film 25a and the polysilicon layer are patterned into a strip having a predetermined width of 11, thereby forming the gate electrode 24 with the remaining polysilicon layer, and the upper surface thereof forms the gate electrode 24. III 2
5 The structure shall be covered by a. Next, the gate oxide film 23a other than under the gate electrode 24 is once removed with dilute hydrofluoric acid and then oxidized again to form an insulation l1l (oxidized DI) 25b on the side surface of the gate electrode Fii24, and at the same time, the gate oxide film 23a is A gate oxide film 23b for a sidewall is formed in the portion where the film has been removed. Here, the thinner the gate oxide film 23b is, the more the electric field near the drain is relaxed and the generation of hot carriers is suppressed.
Forms an oxide film with a relative thickness of about 0.0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 nature form type

In the production of a normal LDD structure MO3FET, phosphorus is then ion-implanted to form an n-layer, but the method of this invention
It is also possible to form an n-layer in the OS FET as well. In this case, since the sidewall is a conductor, there is an advantage that initial deterioration as seen in a normal LDD structure MOS FET does not occur.

However, in this invention, the n-layer is basically unnecessary,
In this manufacturing method and in FIG. 1, no n-layer is formed.

■ Sidewall forming process (Fig. 6) Above substrate 21
After depositing a conductor such as phosphorus-doped polysilicon with a thickness of 2,000 to 8,000 on the entire upper surface, this is anisotropically etched to form a sidewall 26 made of the remaining conductor on the sidewall of the gate electrode 24 (vA edge film). 25b). Next, the side wall 26
Using the gate electrode 24 and field oxide film 22 as a mask, N-type dopants such as phosphorus and arsenic are applied in 1912~
Forming a source diffusion region 27 and a drain diffusion region 28 in the substrate 21 on both sides of the gate structure by ion implantation into the Fi base 21 at a dose of 101 cm-'';
After that, heat treatment for activation is performed, and then the source/drain expansion W1. area 27
．． The oxide film on 28 is removed with dilute hydrofluoric acid.

■ Connecting layer forming process (Figure 7) After depositing a conductor such as phosphorus-doped polysilicon with a thickness of 1,000 to 5,000 layers over the entire surface of the substrate 21, this is patterned by anisotropic etching.
A connection layer 29 is formed. Here, it goes without saying that the connection layer 29 is formed to electrically connect the sidewall 26 made of a conductor and the drain diffusion region 28.

■ M wiring formation process (Fig. 8) Then, after depositing PSG with a thickness of 3,000 to 8,000 as the intermediate insulating film 32 and opening the contact hole 33,
The M wiring 30 is formed by depositing M to a thickness of 000 to 10000 and patterning it.

With the above steps, the MOS FET shown in FIG. 1 is completed.

Note that although the above description has been made regarding an n-channel MO5FET, the present invention can be similarly applied to a p-channel MO3FET.

(Effects of the Invention) As described in detail above, according to the semiconductor device of the present invention, a sidewall is formed on the sidewall of the gate electrode by a conductor insulated from the sidewall, and this sidewall is connected to the drain. Since the potential is the same as that of the drain, the electric field near the drain can be warmed, hot carrier generation can be suppressed, and hot carrier deterioration can be suppressed. Furthermore, since the device of the present invention basically does not require a low-concentration layer with an LDD structure, there is no problem that the miniaturization of elements is limited by diffusion of the low-concentration layer, which is advantageous for miniaturization. Become. Also, even if an LDD structure is adopted, if the sidewall is a conductor, it will not work as a normal LDD.
There is no initial deterioration like that seen with structured MO3FETs,
It can have excellent real carrier resistance.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing one embodiment of the semiconductor device of the present invention, FIG. 2 is an equivalent circuit diagram of the device of one embodiment, FIG. 3 is a pattern plan view of the device of one embodiment, and FIGS. FIG. 8 is a plan view and a cross-sectional view showing the device of one embodiment in the order of manufacturing steps;
Is Figure 9 a conventional LDD structure? FIG. 10 is a cross-sectional view of the structure of the IO5FET, FIG. 1O is a cross-sectional view of the manufacturing process of a conventional LDD structure MO5FET, and FIG. 11 is a characteristic diagram showing the gate voltage dependence of substrate current and transfer conductance deterioration. 21... P-type silicon substrate, 23... Gate oxide film, 24... Gate electrode, 25... Insulating film, 26...
- Side wall, 27... Source diffusion region, 28.
...Drain diffusion region, 29...Connection layer. No. 22 MO5FE Utabetare Plane Mouth Figure 3 of MO5FE Uta Betare Plane Mouth of Sumika Izuki--] – Figures (d) (e) ・Top view of the MO5FET tyr repair process after the LDD disaster Figure 1O It! AVC, (V) Futto electric +: l: vG (V) (a) (b) CO) gpoQ: 10,000t and Q0iΣ溌, ko>gututans 4 汀乀 Nori'! Tokimi 1 (Retshihi L 1st) Figure

Claims (1)

[Claims] (a) a semiconductor substrate; (b) a gate insulating film formed on this semiconductor substrate; (c) a gate electrode formed on this gate insulating film; (d) this gate a sidewall made of a conductor formed on the sidewall of the gate electrode insulated from the electrode and similarly arranged on the gate insulating film; (e) a gate structure having the sidewall and the gate electrode; A semiconductor device comprising: a source diffusion region and a drain diffusion region formed in the substrate on both sides; and (f) a connection layer connecting the drain diffusion region and the sidewall so that they are at the same potential. .