JPH02276272A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device including a high-voltage, high-performance vertical PNP transistor configured to prevent the silisk effect.

[Conventional technology]

Traditionally, bipolar
In CMO3 semiconductor devices, vertical PN is used to increase speed.
Various proposals have been made as means for reducing the collector resistance of a P transistor.

For example, in JP-A-57-157567, the fourth
As shown in the figure, a P-type buried layer 103 serving as a collector region is disposed on the epitaxial layer 106, and a P-type buried layer 103 is arranged on the epitaxial layer 106, and
7 is surrounded by a P-type collector derivation region 105, and further P
A configuration is disclosed in which re-diffusion of the type buried layer 103 toward the substrate 101 is stopped at the epitaxial layer 106 and the N type buried layer 102. In FIG. 4, 104 is an isolation region, and 108 is an emitter region.

[Problems to be Solved by the Invention] Incidentally, in the conventional vertical PNP transistor shown in FIG.
If the IQ is not higher than c+*-', the punch-through voltage of the parasitic PNP transistor cannot be sufficiently increased, and hF[
cannot be sufficiently reduced, but the epitaxial layer 106
If the surface angle of 4° is set to this level, the collector-base parasitic capacitance will increase, and the collector-base breakdown voltage will decrease, which may hinder the performance of the vertical PNP transistor.

Therefore, as in the prior art, an epitaxial layer 106 is formed between the P-type bone M region 104 and the P-type collector derivation region 105.
In the case of a configuration using , there is a problem that it is impossible to obtain a bipolar CMO3 semiconductor device having both analog and digital functions and having a vertical PNP transistor with high breakdown voltage and high performance characteristics.

The present invention was made to solve the above-mentioned problems in conventional bipolar CMO3 semiconductor devices.
It is an object of the present invention to provide a semiconductor device having a vertical PNP transistor having high breakdown voltage and high performance characteristics, which reduces E and prevents parasitic thyristor effects.

Means and operation for solving problem C1) In order to solve the above problems, the present invention provides a semiconductor device including a vertical PNP transistor, in which the vertical PNP transistor is surrounded at a distance around the base region, and the a P-type collector lead-out region formed to reach the P-type buried layer disposed below the base region; and a P-type collector lead-out region surrounding the P-type collector lead-out region;
It is constructed by providing an isolation N-type diffusion region that is formed to reach the N-type buried layer disposed below the P-type buried layer.

By arranging the P-type collector lead-out region so as to surround the base region of the vertical PNP transistor, the collector resistance can be reduced and the parasitic NPN
It is possible to reduce the hyt of the l-run risk, and by arranging the isolation N-type diffusion region around the collector lead-out region, the hyt of the parasitic PNP transistor can be reduced, and the parasitic thyristor effect can be reduced. can be effectively prevented. Therefore, the vertical type P with high withstand voltage and high performance
It becomes possible to easily realize a semiconductor device including an NP transistor.

[Example] Examples will be described below. First, the basic configuration of a 1ii5PNP transistor in a semiconductor device according to the present invention will be explained based on FIG. In Figure 1, 1
is a P-type silicon substrate; 2 is an N-type buried layer selectively formed on the substrate 1;

4 is an epitaxial layer formed of two layers, and 3 is a collector region P formed in the epitaxial Ji4.
This is a mold embedding layer. 6 surrounds the N-type base area 9 and the P
A collector lead-out region is formed to reach the type buried layer 3, and 5 is an N-type isolation region formed to surround the collector lead-out region 6 and reach the N-type buried layer 2. 7
is a P-type well region, 8 is a field oxide film, 10 is a N diffusion layer for the external base region, and 11 is a P type emitter region.
4 diffusion layers.

In this way, the N component M8M area 5 and the P type collector derivation area 6
By forming this, a breakdown voltage between the base and collector of the vertical PNP transistor can be ensured, and at the same time, latch-up of the NPNP thyristor parasitic effect between the base region and the substrate can be prevented.

The collector-base breakdown voltage is determined by the distance between the base region 9 and the P-type collector lead-out region 6 and the concentration of the epitaxial layer 4. Further, the latch-up prevention ability of the parasitic NPNP thyristor is determined by the width and concentration of the P-type collector lead-out region 6 and the N-type isolation region 5.

Therefore, the above-mentioned collector-base breakdown voltage and launch-up prevention ability can be correlated by appropriately setting the distance between the base region and the P-type collector deriving region, and the concentration and width of the P-type collector deriving region and the N-type separation region. Therefore, a digital/analog mixed bipolar/CMO3 semiconductor device including a high-voltage, high-performance vertical PNP (PNP) run lister can be easily obtained.

Next, a specific embodiment of the present invention will be explained based on FIG. 2, showing its manufacturing method. First, an N-type buried layer 2 is selectively formed on a P-type silicon substrate 1 using a well-known method, and then N-type epitaxial growth is performed at a concentration of 0.5 to 3E16 cm-'. A mold embedding layer 3 is formed by ion implantation, and after heat treatment,
A second epitaxial growth is performed to form an epitaxial layer 4.

Next, a vertical P is formed using the same normal photolithography technique.
The N-type isolation region 5 that reaches the N-type buried layer 2 of the NP transistor is divided into a diffusion region for pulling up the collector of a vertical NPN l-run lister, a region for pulling up the N-type buried layer of a P-type diffused resistor (not shown), and a horizontal PNP transistor. Diffusion area for raising the base and horizontal PMO3! - At the same time as the transistor N-well potential raising diffusion region, it is selectively formed by ion implantation. Subsequently, a P-type collector lead-out region 6 reaching the P-type buried layer 3 is selectively formed by ion implantation at the same time as the substrate lifting diffusion region.

The P-type collector lead-out region 6 of the vertical PNP transistor is
In order to reduce the collector resistance and suppress hFt of the parasitic NPN transistor to 10 or less, it is formed to surround the N-base region 9, which will be described later, and the impurity dose is 3×1.
0"cm-" or more. Also, P-type collector derivation region 6
is 1.0 to 1.0 from the base region 9 in order to minimize the expansion of the element area and ensure the withstand voltage between the collector bases.
3.0 μmM, and the region width is 1.0 to 5.0 μm.

Next, P-type well region 7 and N-type well region 12 are selectively formed by ion implantation.

Next, a field oxide film 8 is formed by a well-known selective oxidation method, and then an N-base region 9 of a vertical PNP transistor is formed by photolithography.
After selectively forming the base region 13, PMOS)
A P-diffusion layer (not shown) is selectively formed for controlling the dark value voltage of the Lanristor, and the NMo5t Lanristor and PMOS
) A polysilicon layer 14 is formed on the gate part of the run lister. Next, an N° diffusion layer IO is selectively formed in the external base region of the vertical PNP transistor and the NMO5) source and drain region of the run lister, and then a vertical type PNP transistor is formed. P.N.
P) The emitter region of the runlister, the external base region of the vertical NPN transistor, the emitter region of the horizontal PNP transistor, and PMO3! - Simultaneously and selectively forming P0 diffusion layers 11 in the source and drain regions of the run lister.

Next, after depositing a glabellar film (not shown) by CVD or the like, a window is opened in the emitter region of the vertical NPN (run lister), and As is ion-implanted to form the emitter region 1.
Then, windows for each contact are opened and metallization is performed to complete the bipolar CMO3 semiconductor device as shown in the figure.

FIG. 3 is a sectional view showing only the vertical PNP transistor portion of the second embodiment. In the basic configuration shown in FIG. 1 and the first embodiment shown in FIG. 2, the parasitic NP of the vertical PNP transistor
N type isolation region 5 for reducing haf of N transistor,
Although shown in FIG.
and N-type isolation region 5 are in contact with each other. Even if they are arranged in contact with each other in this manner, the same effects as in the first embodiment can be obtained, and the expansion of the element area can be minimized.

Each of the above embodiments is a vertical NPN transistor, ¥4 type P
NP transistor, lateral PNP transistor.

Although the present invention has been applied to a semiconductor device including a horizontal CMO3 transistor, the present invention is applicable to a semiconductor device including a vertical CMO3 transistor, for example.
It can also be applied to devices with various combinations, such as a combination of an N transistor and a lateral PNP transistor. Furthermore, the present invention can also be applied to semiconductor devices that include other passive elements in addition to these elements.

〔Effect of the invention〕

As described above based on the embodiments, according to the present invention, in a vertical PNP transistor, the P-type collector lead-out region is provided so as to surround the base region at a distance, thereby reducing collector resistance and reducing parasitic The hrt of the NPN transistor can be reduced, and the N-type isolation region is placed around the P-type collector lead-out region.
It is possible to reduce the hFE of the parasitic PNP transistor and effectively prevent the parasitic si-risk effect. Therefore, a semiconductor device having a vertical PNP transistor with high breakdown voltage and high performance can be easily obtained.

[Brief explanation of drawings]

FIG. 1 shows a vertical PNP in a semiconductor device according to the present invention.
Figure 2 is a cross-sectional view showing the basic configuration of l-run risk.
FIG. 3 is a cross-sectional view showing the first embodiment of the present invention; FIG. 3 is a cross-sectional view showing the vertical PNP transistor portion of the second embodiment;
The figure is a cross-sectional view showing an example of the structure of a conventional vertical PNP transistor. In the figure, l is a P-type substrate, 2 is an N-type buried layer, 3 is a P-type buried layer, 4 is an epitaxial layer, 5 is an N-type isolation region, 6
Reference numeral 1 indicates a P-type collector lead-out region, 7 a P-type well region, 8 a field oxide film, 9 an N-base region, and 10 an N°-type scattering layer 11 a P9-type diffusion layer.

Claims (1)

[Scope of Claims] 1. A P-type collector lead-out region surrounded by a spaced apart space around a base region and formed to reach a P-type buried layer disposed below the base region; and the P-type collector lead-out region. A semiconductor comprising a vertical PNP transistor having an isolation N-type diffusion region surrounding the region and reaching an N-type buried layer disposed below the P-type buried layer. Device. 2. The semiconductor device according to claim 1, wherein the P-type collector lead-out region and the isolation N-type diffusion region of the vertical PNP transistor are arranged in contact with each other. 3. The P-type collector lead-out region in the vertical PNP transistor is 1-3 μm apart from the base region and 1-5 μm apart.
The width of the isolation N-type diffusion region is 1 to 5μ.
3. The semiconductor device according to claim 1, wherein the semiconductor device is formed with a width of m. 4. The vertical PNP transistor has an impurity dose of 3×10^1^3cm^-^2 in the P-type collector lead-out region.
With the above, h_F_E of the parasitic NPN transistor is 10
4. The semiconductor device according to claim 1, wherein the semiconductor device has the following characteristics. 5. The vertical PNP transistor according to any one of claims 1 to 4, the vertical NPN transistor, and the horizontal PNP
A semiconductor device characterized by monolithically forming a transistor and a lateral CMOS transistor. 6. The semiconductor device according to claim 5, wherein the P-type collector lead-out region of the vertical PNP transistor and the substrate lifting region are selectively formed of the same diffusion layer. 7. An N-type diffusion region for isolation of the vertical PNP transistor, a collector pull-up diffusion region of the vertical NPN transistor, and an N-type buried layer pull-up region of the P-type diffused resistor;
7. The semiconductor device according to claim 5, wherein the diffusion region for raising the base of the lateral PNP transistor and the diffusion region for raising the N-well potential of the lateral PMOS transistor are selectively formed of the same diffusion layer.