JPH02276334A - Synchronization detector - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization detection device used in a multi-channel access system e.

[Conventional technology]

Figure 9 is a block diagram showing, for example, the conventional synchronization detection method shown in the "Appendix to the Report on the Development Study of Multi-Channel Access Systems" (March 1980, Mobile Radio Center). Yes, in the figure,
1 is an input terminal into which received data is input; 2a is a synchronization pattern detection circuit connected to this input terminal 1 and detects a synchronization pattern in the received data; 3 is this synchronization pattern detection circuit 2a and the input terminal 1; This is a data processing circuit connected to the synchronization pattern detecting circuit 2a, which analyzes the synchronization pattern and instructs the synchronization pattern detection circuit 2a to search for the next synchronization pattern.

Next, the operation will be explained. Reception data received at input terminal l is input to synchronization pattern detection circuit 2a and data processing circuit 3. The synchronization pattern detection circuit 2a searches this input received data and detects whether a synchronization pattern exists in the received data. When the synchronization pattern detection circuit 2a discovers a synchronization pattern in the received data, it notifies the data processing circuit 3 to that effect. The data processing circuit 3 analyzes the received data following the discovered synchronization pattern.

As a result of the analysis, if it is determined that the discovered synchronization pattern is the correct synchronization pattern, the data processing circuit 3 continues processing the data received from the input terminal 1. When the process is completed and it is necessary to search for a new synchronization pattern in order to receive the next received data, the synchronization pattern detection circuit 2
Instruct a to start a synchronization pattern search. Further, as a result of the analysis, if the synchronization pattern is incorrect due to the influence of noise, the data processing circuit 3 instructs the synchronization pattern detection circuit 2 to start searching for a new synchronization pattern.
give to a.

FIG. 1A is a circuit diagram showing an example of the configuration of the synchronization pattern detection circuit 2a. In the figure, 21 is a shift register that shifts received data one bit at a time, and 22 is a shift register that shifts received data bit by bit. It is a coincidence detection circuit that compares the output of the register 21 and the fixed pattern storage section 2.
3 has the same pattern as the synchronization pattern. According to this configuration, when the received data inputted from the input terminal 1 matches the pattern in the fixed pattern storage section 23, a matching signal as shown in FIG. 2(B) is output. and,
This coincidence signal is notified to the data processing circuit 3, and the data processing circuit 3 can be informed of the discovery of the synchronization pattern.

[Problem to be solved by the invention]

Since the conventional synchronization detection device is configured as described above, when the synchronization pattern detection circuit 2a mistakenly detects a synchronization pattern due to noise etc., the data processing circuit 3 analyzes it to determine that it is an incorrect synchronization pattern. Even if the correct synchronization pattern is found, the correct synchronization pattern may have been missed at that point, resulting in a problem of poor reception rate.

This invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a synchronization detection device that can reliably detect the correct synchronization pattern immediately after it when an incorrect synchronization pattern is detected without missing it. shall be.

[Means to solve the problem]

The synchronization detection device according to the invention described in claim (1) searches for a synchronization pattern in received data, and when a synchronization pattern is found, detects the position of the synchronization pattern, and
A synchronization pattern detection circuit that, when informed by the data processing circuit that an incorrect synchronization pattern has been detected, starts searching for a synchronization pattern from the next position of the synchronization pattern using a research means, and the research means is the target of the search. and a synchronous position storage means for storing position information for the re-search means to start searching.

The synchronization detection device according to the invention described in claim (2) searches for a synchronization pattern in received data, and when a synchronization pattern is found, detects the position of the synchronization pattern, and
Even after detecting synchronization patterns by parallel search means,
A synchronization pattern detection circuit that continues searching for a synchronization pattern from the next position of the synchronization pattern, and a synchronization position storage means that sequentially stores position information indicating the position in the received data of the synchronization pattern obtained as a result of the search. It is something that

[For production]

The synchronization pattern detection circuit in the invention according to claim (1) searches for a synchronization pattern in received data, and when a synchronization pattern is found, notifies the data processing circuit to that effect and detects the position of the synchronization pattern, The invention according to claim (2), wherein when the data processing circuit that analyzes the received data following the synchronization pattern is informed that an incorrect synchronization pattern has been detected, the synchronization pattern is searched from the next position of the synchronization pattern. When the synchronization pattern detection circuit starts searching for the synchronization pattern of the received data, it stores all position information indicating the position of the synchronization pattern detected thereafter in the synchronization position storage means.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is an input terminal, and 3 is a data processing circuit, which are the same or equivalent parts to those of the conventional circuit which are denoted by the same reference numerals in FIG. 8, and detailed explanation thereof will be omitted.

Further, 2 is a synchronization pattern detection circuit having a re-search means, and 4 is a reception data memory (4) that stores the received data input from the input terminal 1 and sends it to the synchronization pattern detection circuit 2.
Storage means), 5 is a synchronization pattern position register (synchronization position storage means) for storing the position of the synchronization pattern detected by the synchronization pattern detection circuit 2.

Next, the operation will be explained. Reception data received at the input terminal 1 is temporarily stored in the reception data memory 4. The synchronization pattern detection circuit 2 reads this received data from the reception data memory 4 and searches for a synchronization pattern. As a result, when a synchronization pattern is found in the received data, the synchronization pattern detection circuit 2 records the position of the synchronization pattern in the synchronization pattern position register 5 and notifies the data processing circuit 3 that the synchronization pattern has been found. The data processing circuit 3 analyzes the received data following the synchronization pattern to determine whether or not it is the correct synchronization pattern.

As a result of the analysis, if the synchronization pattern is correct, the data processing circuit 3 processes the received data. When the process is completed and a search for a new synchronization pattern is necessary to receive the next received data, the data processing circuit 3 instructs the synchronization pattern detection circuit to start a synchronization pattern search. In accordance with the instruction, the synchronization pattern detection circuit 2 starts searching for a synchronization pattern from the sent position.

Further, as a result of the analysis, if the synchronization pattern is incorrect due to the influence of noise, etc., the data processing circuit 3
gives an instruction to the synchronization pattern detection circuit 2 to start searching for a new synchronization pattern. According to the instruction, the synchronization pattern detection circuit 2 detects the next synchronization pattern from the next position of the synchronization pattern recorded in the synchronization pattern position register 5, targeting the received data stored in the reception data memory 4. Start your search.

When a new synchronization pattern is discovered, the synchronization pattern detection circuit 2 records the position of this new synchronization pattern in the synchronization pattern position register 5 and notifies the data processing circuit 3 of the position. The data processing circuit 3 receives the data from that location in the received data memory 4, and
Received data can be analyzed.

FIG. 2 is an explanatory diagram for explaining the re-search operation of the synchronization pattern detection circuit 2. The re-search operation will be explained in more detail with reference to the figure. First, synchronization pattern detection circuit 2
inputs data from the received data memory 4 and searches for a synchronization pattern. When a synchronization pattern is detected, this is notified to the data processing circuit 3, and the corresponding address in the received data memory 4 is recorded in the synchronization pattern position register 5 (operation at point A in the figure). The data processing circuit 3 takes this as an opportunity to start the above-mentioned analysis operation, and when it is determined that the synchronization pattern is an erroneous pattern, it notifies the synchronization pattern detection circuit 2 to that effect (point B in the figure). The synchronization pattern detection circuit 2 is connected to the received data memory 4.
When a new synchronization pattern is detected, the data processing circuit 3 is notified of the fact and its location (point C in the figure). ). Therefore, the data processing circuit 3 starts analyzing the received data again (point E in the figure). Then, the received data following the new synchronization pattern (portion F in the figure) can be retrieved from the received data memory 4 for analysis.

FIG. 3 is a circuit diagram showing an example of the synchronization pattern detection circuit 2. In the figure, reference numeral 4 denotes a received data memory consisting of a 2-vote memory of 1 bit x N addresses, and 24
25 is a reception address control circuit that provides a corresponding write address and a write signal to one port of the reception data memory 4; and 25 is a read address control circuit that provides a corresponding read address and read signal to the other port of the reception data memory 4. , 26 are switches for switching whether to apply the data read from the received data memory 4 to the data processing circuit 3 or to the shift register 21.

Next, the operation will be explained. First, the contents of the reception address counter of the reception address control circuit 24 and the read address counter of the read address control circuit 25 are cleared. Then, the received data inputted from the input terminal 1 is sequentially transferred bit by bit to the received data memory 4.
will be written to. At this time, the reception address control circuit 24
introduces a clock signal synchronized with the received data, provides the contents of the received address counter to the received data memory 4 in synchronization with this clock signal, and simultaneously outputs a write signal to control the write address. and,
Increment the contents of the reception address counter (N
If so, return it to 0).

On the other hand, the read address control circuit 25 can know whether the received data has been recorded in the received data memory 4 by comparing the contents of the received address counter and the read address counter. When it is recognized that the received data has been recorded in the received data memory 4, the received data memory 4
Start read control. At first, it is necessary to search for a synchronization pattern, so the read address control circuit 25 switches the switch 26 to the shift register 21 side.

Then, the content of the read address counter is given to the reception data memory 4, and at the same time, a read signal is output. Next, the contents of the read address counter are incremented. By repeating these operations, the contents of the received data memory 4 are sequentially read out. The read data is input to the shift register 21. Here, the read address control circuit 25 provides the shift register 21 with a shift clock synchronized with the data. Shift register 21, -
The number output circuit 22 and the fixed pattern storage section 23 operate in the same manner as in the conventional case, and send the coincidence signal to the data processing circuit 3.
Output to. This match signal also introduces the read address control circuit 25. Then, read address control circuit 2
5 switches the switch 26 to the data processing circuit 3 side when a matching signal is detected. At the same time, the value of the read address counter at this time is recorded in the synchronization pattern position register 5. Thereafter, the data read from the received data memory 4 is manually input to the data processing circuit 3. Data processing circuit 3
As a result of data analysis, if it is determined that the synchronization pattern is incorrect, it outputs a re-search request signal 27. When the read address control circuit 25 detects this re-search request signal 27, it retrieves the value recorded in the synchronization pattern position register 5 and sets it in the read address counter, and at the same time switches the switch 26 to the shift register 21 side.

As a result, the data stored in the received data memory 4 can be searched from the address next to the address where the erroneous synchronization pattern is stored.

Note that when the data processing circuit 3 analyzes the data and determines that it is a correct synchronization pattern and completes the data processing, the data processing circuit 3 outputs a reset signal. The read address control circuit 25 detecting this reset signal starts the next synchronization pattern search operation.

Furthermore, the synchronization pattern detection circuit 2 can be realized by a microprocessor sensor. FIG. 4 shows the synchronization pattern detection circuit 2, data processing circuit 3, and synchronization pattern position register 5.
1 is a diagram showing an example of a configuration in which a PUI 1 and a program memory (ROM) 12 are configured, and a received data memory 4 is configured by a RAM 13. FIG. According to this configuration, first, received data inputted from the input terminal 1 is converted by the serial/parallel converter 14 into parallel data (for example, 8 bits) having the data bus width of the bus 15. Then, when the '8 bits are complete, an interrupt signal is sent to CPUI1.

In response to this interrupt signal, the CPU II receives data from the serial/parallel converter and stores it in the RAM 13. Thereafter, the operations of the synchronization pattern detection circuit 2 and the data processing circuit 3 realized as a program in the ROM 12 are executed. Synchronous pattern position register 5 is CP
Allocate it to an appropriate register among the registers existing in U1l.
If I1 is adopted, the serial/parallel converter 14 does not need to be provided.

FIG. 5 is a block diagram in the case where the synchronization pattern position register 5 is provided at a position where the data processing circuit 3 can input the contents of the synchronization pattern position register 5. In this case, the received data input from the input terminal 1 is configured to pass through the synchronization pattern detection circuit 2. The operation when configured in this way will be explained with reference to the explanatory diagram of FIG. 6. First, the synchronization pattern detection circuit 2 stores received data input from the input terminal 1 in the received data memory 4, and searches the received data in order to detect a synchronization pattern. When the synchronization pattern is detected, the position where the synchronization pattern is stored in the received data memory 4 is recorded in the synchronization pattern position register 5 (point G in the figure). Here, when a synchronization pattern is detected for the first time, storage in the received data memory 4 may be started. Data processing circuit 3
By constantly checking the synchronous pattern position register 5, the user can know that position information indicating the position of the same month pattern has been recorded. When recognizing that the position information has been recorded, the data processing circuit 3 starts an analysis operation, receives data following the synchronization pattern from the received data memory 4, and analyzes the data. - On the other hand, the synchronization pattern detection circuit 2 searches the received data even after detecting the synchronization pattern, and when a new synchronization pattern is detected (point H in the figure), the position information is already recorded in the synchronization pattern position register 5. Record the position of the new synchronization pattern in the next area. When the data processing circuit 3 determines that the previously detected synchronization pattern is incorrect as a result of analysis (1 point in the figure),
The new synchronization pattern position information is entered manually from the second area of the synchronization pattern position register 5. Then, analysis is performed again from the next data at that position in the received data memory 4. Incidentally, if the function of the synchronous pattern position register 50 is included in the data processing circuit 3, a configuration as shown in FIG. 7 can be obtained. In this case, the synchronization pattern detection circuit 2 sequentially outputs position information indicating the position of the synchronization pattern to the data processing circuit.

In FIG. 8, F I is used instead of the synchronization pattern position register 5.
FIG. 2 is a block diagram showing a case where an FO (First In First Out) memory 5a is provided. In this case, the synchronization pattern detection circuit 2 sequentially inputs position information indicating the position of the detected synchronization pattern to the FIFO memory 5a. Then, the data processing circuit 3 connects to the FI when necessary.
It is sufficient to input position information from the beginning position of the FO memory 5a. In this case, the data processing circuit 3 can save the effort of obtaining the position information by considering the area in the register, as in the case shown in FIG. In the case of this embodiment, the received data memory 4 is not required in order to detect the position of the synchronization pattern in the received data, so it is not shown in FIG. However, data processing circuit 3
However, in order to analyze the received data that has already been manually input from the input terminal l, a memory is necessary, and the received data is stored in the data processing circuit 3. In other words, the position information output by the synchronization pattern detection circuit 2 indicates the position in the memory of the data processing circuit 3. For the same reason, the received data memory 4 may be removed from the configurations shown in FIGS. 5 and 7, and the data processing circuit 3 may have a memory for data analysis and data processing.

〔Effect of the invention〕

As described above, according to the present invention, when a synchronization pattern is erroneously detected, the search for a correct synchronization pattern is started from the position next to the erroneously detected synchronization pattern. , Since we configured the system to continue searching for a synchronization pattern even after the first synchronization pattern is detected, the probability of missing a correct synchronization pattern when a synchronization pattern is detected incorrectly is significantly reduced.
This has the effect of preventing a decrease in reception rate.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a synchronization detection device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram for explaining a synchronization pattern re-search operation, and FIG. 3 is a circuit showing an example of a synchronization pattern detection circuit. 4 is a block diagram showing the configuration of a synchronization detection device implemented by a microprocessor, FIG. 5 is a block diagram showing a synchronization detection device according to another embodiment of the present invention, and FIG. 6 is a parallel search operation. Explanatory diagram for explaining, 7th
8 and 8 are block diagrams showing a synchronization detection device according to still another embodiment of the present invention, FIG. 9 is a block diagram showing a conventional synchronization detection device, and FIG. 10 shows a conventional synchronization pattern detection circuit. It is a circuit diagram. 1 is an input terminal, 2 is a synchronization pattern detection circuit including re-search means or parallel search means, 3 is a data processing circuit, 4 is a received data memory (storage means), 5 is a synchronization pattern position register (synchronization position storage means), 5a is FIFO memory (
synchronous position storage means). In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (2)

[Claims] (1) A synchronization pattern detection circuit that searches received data and detects a synchronization pattern therein; and a synchronization pattern detection circuit that analyzes the received data following the synchronization pattern detected by the synchronization pattern detection circuit; A synchronization detection device comprising a data processing circuit for instructing a search for the next synchronization pattern, a storage means for storing the received data, and storing position information indicating the position of the synchronization pattern detected by the synchronization pattern detection circuit. and synchronization position storage means, when the synchronization pattern detection circuit is instructed to search for the synchronization pattern by the data processing circuit that has detected that the synchronization pattern is incorrect through the analysis, the synchronization position storage means A synchronization detecting device comprising: a re-search means for starting a re-search for a synchronization pattern based on position information stored in the synchronization position storage means for received data stored in the synchronization detection means. (2) a synchronization pattern detection circuit that searches received data and detects a synchronization pattern therein; and a synchronization pattern detection circuit that analyzes the received data following the synchronization pattern detected by the synchronization pattern detection circuit; A synchronization detection device comprising: a data processing circuit for instructing a search for the next synchronization pattern, further comprising a synchronization position storage means for storing position information indicating the position of the synchronization pattern detected by the synchronization pattern detection circuit; In the detection circuit,
In parallel with the analysis of the data processing circuit, a new synchronization pattern is searched for in the received data following the detected synchronization pattern, and position information indicating the position of the new synchronization pattern obtained as a result of the search is used as the synchronization position. A synchronization detection device comprising a parallel search means stored in a storage means.