JPH02277265A - Input protecting circuit for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the gate of a protective transistor from breaking down by providing resistors between the gate of a p-type transistor for forming an input protective circuit, power source potential wirings, and the gate of an n-type transistor and a ground potential wiring. CONSTITUTION:An n-type transistor 4 is formed in a first region 2 of the surface of a p-type Si substrate 1, a p-type transistor 5 is formed in an n-well region 3 (second region), and an input terminal 8 and drains 4d1, 4d2, 5d1, 5d2 are connected. Source 4S, 5S are respectively connected to ground potential wiring 6 and power source potential wiring 7, gate 4g1, 4g2 are connected to a p-type Si substrate 1 via a contact hole 4gc, and gate 5g1, 5g2 are connected to a n-well region 3 through a contact hole 5gc. Thus, since the resistor R1 of the substrate 1 and the resistor R2 of the n-well region are interposed on a circuit, even if a high voltage such as static electricity, etc., is applied to a power source terminal and a ground terminal, the gates of the transistors 4, 5 can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input protection circuit, and particularly to an input protection circuit for a semiconductor integrated circuit.

[Conventional technology]

Conventionally, in this type of input protection circuit, the drains of a p-type transistor 5 and an n-type transistor 4 are connected to an input terminal 8, as shown in FIG. 3, and the circuit functions as an internal circuit protection element. . p-type transistors 5 and n
In order to keep the type transistor 4 (hereinafter referred to as a protection transistor) in an off state, each gate is fixed to the power supply potential and the ground potential, and the input terminal 8 is exposed to momentary positive and negative high voltages due to static electricity, etc. When voltage is applied,
The input terminal is protected using the breakdown phenomenon of transistors.

In other words, when a positive high voltage is applied to the input terminal, the pn between the drain of the n-type transistor 4 and the n-type semiconductor substrate
Due to the reverse breakdown phenomenon of the junction, or when a high negative voltage is applied to the input terminal, the reverse breakdown phenomenon of the pn junction between the drain of the n-type transistor and the n-well region clamps the voltage and directs the current to the outside. I was trying to escape.

[Problem to be solved by the invention]

In the conventional input protection circuit described above, as shown in FIG. 3(b), the power supply terminal and the ground terminal are directly connected to the gate of the protection transistor by Ag wiring (power supply potential wiring 7 and ground potential wiring 6). , when high voltage such as static electricity is applied to these two terminals, the withstand voltage of the gate insulating film is 30
Currently, it is common to be designed for ~40V, but there is a drawback that the gate of the protection transistor is destroyed.

[Means to solve the problem]

The input protection circuit for a semiconductor integrated circuit of the present invention includes a first transistor of a second conductivity type provided in a first region of a surface portion of a semiconductor substrate of a first conductivity type; a second transistor of the first conductivity type provided in a second region of the second conductivity type provided in the second region, the input terminal and the drain sides of the first transistor and the second transistor are connected; The source side of the second transistor is connected to the power supply potential wiring, the source side of the first transistor is connected to the ground potential wiring, and the gate electrode of the second transistor is connected between the power supply potential wiring and the second region. The gate electrode of the first transistor is connected to the second region through a contact hole independent of the contact hole, and the gate electrode of the first transistor is connected to the first region through the contact hole independent of the contact between the ground potential wiring semiconductor substrates. It is said that it is connected to the area of .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1(a) is a pattern diagram of one embodiment of the present invention.

This embodiment includes an n-type transistor 4 (first transistor) in a first region 2 on the surface of an n-type S1 substrate 1 and an n-type transistor 5 (second transistor) in an n-well region 3 (second region). transistor), and the input terminal 8 and the first . Second
The drains of the transistors 4dl, 4d2.5dl, 5
d2 is connected, the sources 4S and 5S are connected to the ground potential wiring 6 and the power supply potential wiring 7, respectively, and the gate 4g14g2
is connected to the n-type Si substrate 1 via the gate-substrate contact hole 4gc, and the gate 5g1.5g2 is connected to the gate-substrate contact hole 4gc.
The n-well region (
3), and these transistors are used as input protection elements.

In this embodiment, the gate potentials of the two protection transistors are at the ground potential and the power supply potential, respectively, so the protection transistors are in an off state, and even if a high voltage such as static electricity is applied to the input terminal 8, the voltage is clamped due to the transistor breakdown phenomenon. It plays a protective role by preventing current from flowing into the internal circuit.

In addition, as in the conventional example, the ground potential wiring 6 and the power potential wiring 7
and the gate of the transistor 4g1.4g2.5g respectively
l, 5g2 is not directly connected, contact hole 4g
The respective gates are connected to the substrate 1 and the n-well region 3 by c and 5gc, and the resistor R1 of the n-type Si substrate and the resistor R2 of the n-well region are interposed in the circuit as shown in FIG. 1(b). Even if a high voltage such as static electricity is applied to the power supply terminal and the ground terminal, it will not be applied directly to the gate, thereby preventing gate breakdown of the protection transistor.

FIG. 2<a) is a pattern diagram of a second embodiment of the present invention.

Almost the same as shown in FIG. 1, n-type and n-type protection transistors 5 and 4 are connected to the input terminal 8 to prevent electrostatic damage to the input terminal. Further, polysilicon resistors '3gp' and '4gp' each having an extended gate are connected to an n-type Si substrate 1 and an n-well region 3, respectively, and a contact hole 5gc,
Since it is electrically short-circuited by 4gc, the circuit diagram becomes as shown in Fig. 2(b), and the resistors R1' and R2' are connected to the gate of the protection transistor, which is different from the first embodiment. In comparison, even when high voltage such as static electricity is applied to the power supply terminal ground terminal, the CR time constant becomes large and the signal transmission time becomes slower. This has the advantage that the gate insulating film of the protection transistor does not need to be destroyed because a breakdown phenomenon occurs and the voltage is clamped and the current is released to the outside.

〔Effect of the invention〕

As explained above, the present invention provides resistors between the gate of the p-type transistor and the power supply potential wiring and the gate of the n-type transistor and the ground potential wiring, which constitute the input protection circuit. This also has the effect of improving the electrostatic breakdown resistance of the ground terminal and the ground terminal.

[Brief explanation of drawings]

FIG. 1(a) is a pattern diagram showing the main parts of the first embodiment of the present invention, FIG. 1(b) is a circuit diagram of the first embodiment of the present invention, and FIG. 2(a) is a pattern diagram showing the main parts of the first embodiment of the present invention. A pattern diagram of the second embodiment of the invention, FIG. 2(b) is a circuit diagram of the second embodiment of the invention, and FIG.
FIG. 3(a) is a pattern diagram of a conventional example, and FIG. 3(b) is a circuit diagram of a conventional example. 1... p-type St substrate, 2... first region, 3...
2nd region (n-well region), 4... n-type transistor (first transistor), 4d1.4d2... drain, 4dc... contact hole between drain electrode and drain region, 4gl, 4g2...・・Gate, 4sc・・
・Contact hole between gate and substrate, 4s...source,
5...p-type transistor (second transistor>, 5
dl, 5d2...Drain, 5s...Source, 5s
c...Contact hole between source electrode and source region, 5
gl, 5g2.5g...gate, 5sc...contact hole between gate and n-well region, 6...ground potential wiring, 6c...ground potential wiring-p+ type contact region 1
Contact hole between 1, 7...power supply potential wiring, 7c...
・Contact hole between power supply potential wiring and 〇+ type contact region 12, 8...Input terminal (ponding pad), 9
. . . Transistor of internal circuit, 10 . . Wiring to internal circuit, 11 . . P + type contact region, 12 .
n+ type contact region.

Claims (1)

[Claims] A first transistor of a second conductivity type provided in a first region of a surface portion of a semiconductor substrate of a first conductivity type; and a second transistor of a second conductivity type selectively provided in a surface portion of the semiconductor substrate. a second transistor of a first conductivity type provided in a region, an input terminal is connected to the drain sides of the first transistor and the second transistor, and a source side of the second transistor is connected to a power supply potential wiring. The source side of the first transistor is connected to the ground potential wiring, and the gate electrode of the second transistor is connected to the ground potential wiring through a contact hole independent of the contact hole between the power potential wiring and the second region. The gate electrode of the first transistor is connected to the first region through a contact hole that is independent of the contact between the ground potential wiring and the semiconductor substrate. Input protection circuit for semiconductor integrated circuits.