JPH02277309A - Digital signal processing unit - Google Patents

Abstract

PURPOSE:To prevent the deterioration in the signal by operating a function of a difference between an absolute level of an input signal and a reference level. CONSTITUTION:An absolute value circuit 39 detects an absolute value L10 of an input signal Xin and a comparator 40 inactivates a comparator 42 when the said level is smaller than a reference level L0 to throw a switch 41 to the upper position shown in figure. A polarity discrimination circuit 37 throws a switch 38 to the lower position shown in figure when the polarity of the input signal Xin is positive and throws the switch 38 to the upper position shown in figure when the polarity of the input signal Xin is negative. Thus, an adder circuit 34 sends an output difference between attenuators 32 and 33. When the absolute value L10 is larger than the reference level Lo, the comparator 40 throws the switch 41 to the lower position in figure to activate the comparator 42. When the absolute value L10 is smaller than the reference level L1 (L0<L1), the switch 43 is thrown to the position of the left contact. Since the coefficient of a coefficient circuit 48 is set to zero, an output of a multiplier 47 is zero and the adder circuit 34 outputs an output of the attenuator 32 as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal processing device suitable for use when performing limiter processing or compressor processing on a digital audio signal such as a PCM audio signal.

[Conventional technology]

Traditionally, audio signals were recorded and played back in analog format, but in recent years compact discs, 8mm VTRs, and R-DA
Devices such as "T" have become popular, and since audio signals are recorded and played back digitally in these devices, it has become possible to enjoy higher quality sound.

[Problem to be solved by the invention]

However, even in these devices, when an audio signal is subjected to limiter processing or compressor processing, for example, this is performed in an analog manner. Therefore, the signal deteriorates and the original function of digitally recording and reproducing signals is impaired.

Therefore, the present invention processes signals digitally,
This prevents signal deterioration.

[Means to solve the problem]

One digital signal processing device of the present invention includes a comparison means for comparing the level of the input signal with a predetermined reference level, and a function related to the difference between the level of the input signal and the reference level when the level of the input signal is higher than the reference level. a calculating means for calculating the polarity of the input signal; a determining means for determining the polarity of the input signal; an addition/subtracting means for adding or subtracting the input signal and the output of the calculating means in accordance with the output of the determining means; and a multiplication means for multiplying by a gain coefficient.

[Effect]

When the level Li of the input signal xi is higher than the reference level Lth, a power function regarding the difference between the two, for example, the formula k (L
i −Lth)n is calculated. Here, k is a predetermined coefficient, and n is an integer greater than 1. This calculated value is the input signal x
It is subtracted from i (Xi-1((Li-Lth)n) and output.The level LL of the input signal xi is the reference level Lt.
When it is smaller than h, for example, the input signal xi is output as is.

Therefore, the input signal can be digitally limited or compressed, reducing the possibility of signal deterioration.

〔Example〕

FIG. 2 is a block diagram of an audio signal processing device to which the digital signal processing device of the present invention is applied.

A digital signal input from the terminal 11 is demodulated into, for example, an NRZ signal in the receiving section 12.

In the case of the so-called self-clock system, the receiving section 12 extracts a clock component from the received data and supplies it to the PLL circuit 13. PLT, the circuit 13 generates continuous clock pulses in synchronization with this input clock, and the receiving section 12
supply to. The PLL circuit 13 performs demodulation in synchronization with this clock pulse, and sends the demodulated data to a digital signal processor (DSP) 14. Ll, 14R1 is supplied to input terminal a (the other input terminal a2 is not used in this embodiment). The DSP 14L performs equalizer processing on the left channel audio signal of the left and right stereo signals, and the DSPI 4R performs equalizer processing on the right channel audio signal, for example, by performing an FIR digital filter operation, and outputs them from terminals S and C.

The data output from the output terminals of DSP14L1 and DSP14R1 is sent to DSP14. Input terminal a1 of L2 and 14R2
The data output from output terminals C of DSP14L1 and 14R1 is supplied to DSP14R2 and 14L2.
are respectively supplied to input terminals a2 of. DSP14L2 and 1
4R2 subjects the left and right channel signals to limiter processing or compressor processing and outputs them from output terminal C. The data output from these DSPIs 4L, 14R2 is input to the transmitter 20, where it is modulated again into a predetermined format suitable for transmission (for example, pi-phase modulation), and is sent to the terminal 2.
1, the signal is serially output to a circuit (for example, a digital amplifier) not shown.

The receiving section 12 includes the DSPs 14L to 14R2 and the transmitting section 20.
The system clock XCLK, synchronization signal 5YNC, etc. necessary for processing are supplied to

The operation section 15 has a plurality of push button switches (not shown), which are operated to obtain desired equalizer characteristics, limiter characteristics, or compressor characteristics. C.P.U.I.
7 shows the display corresponding to this operation on CRT, lamp, and LED.
The ROM1 is displayed on the display unit 16 consisting of
A predetermined program is read from the DSP 14L to 14R2, and various control signals are outputted to the DSP 14L to 14R2 to control them in order to realize specified characteristics. At this time, RAMl
9, necessary data is stored and read out.

FIG. 3 is a flowchart showing the operation of the CPUI 7. As shown in figure (a), when starting, first C
PU17 is initialized (step 101), then D
S P 14 Ll to 14R2 are initialized (
Step 102). Next, the operating states of the plurality of pushbutton switches in the operating section 15 are determined (step 103), and when they are off, the state of waiting for a certain period of time is repeated (step 104).

When the pushbutton switch is turned on, the set value of the pushbutton switch is read (step 105). Next, among the parameters (used for signal processing) stored in advance in the ROM 18, those corresponding to the operation of the push button switches are selected, and these are sequentially transmitted to the DSPs 14L to 14R2.
A built-in parameter memory 79 (seventh
(see figure) along with the address information (steps 106, 107, 108). Subsequently, the CPU 7 generates a switching signal AD (step 109), and further sends data to the display section 16 (step 110).

FIG. 3(b) shows the interrupt routine.

When an interrupt occurs, the CPU 17 generates a pulse C8d (step 201) and returns to the main routine.

This pulse is sent from the CPU 17 to the receiving section 12 at predetermined time intervals.

FIG. 1 is a functional block diagram of limiter characteristics or compressor processing executed in the DSP 14L2 or 14R2.

The input signal (digital full data) xjn input to the input terminal 31 is attenuated by a predetermined level by an attenuator (ATT) 32 and then input to the addition/subtraction circuit 34 . Also, the output of attenuator 32 is
3, the switch 4 is further attenuated by a predetermined level.
1 (upper side in the figure).

The input signal xin is also input to an absolute value circuit (ABS) 39, and the absolute value Lin of its level is detected and output.

The comparator (GOMP) 40 is at the level L of this absolute value.
In is the predetermined standard value. Compared to the above, the level Lin is at the standard value. When it is smaller, the comparator 42 is made inactive and the switch 41 is switched to the upper side in the figure. As a result, the output of attenuator 33 changes to switch 4.
1 is supplied to the switch 38.

The polarity determining circuit 37 determines the polarity (positive or negative) of the input signal xin, and switches the switch 38 to the lower side in the figure when it is positive and to the upper side in the figure when it is negative. Therefore, the addition/subtraction circuit 34
outputs the outputs of attenuators 32 and 33. Attenuators 32 and 3 are applied so that this output becomes a sufficiently small value.
3 has been adjusted, the level of the signal output from the terminal 36 at this time becomes almost zero. That is, as shown in FIG. 4, the output characteristic in this case corresponds to the γ region (signal non-passage region). In other words, since the level of the input signal is low in this case, the output is gated as noise.

On the other hand, the absolute value level Lin of the input signal xin is the reference level L. When the comparator 40 is greater than the switch 41
is switched to the lower side in the figure, and the comparator 42 is put into operation. The comparator 42 has an absolute value level Li
n is a predetermined reference level L.

(Lo<L□), and when it is smaller than the reference level L1 (L, <Lin<L), the switch 43 is switched to the contact on the left side in the figure. Coefficient k of coefficient circuit 48. is set to the value O. Therefore, since the output level of the multiplier 47 becomes zero at this time, the addition/subtraction circuit 34 outputs the output of the attenuator 32 as is. That is, the output characteristic in this case corresponds to the region β (linear region) in FIG.

The absolute value level Ljn is larger than the reference level L□ (Li
n≧L), the switch 43 is switched to the coefficient circuit 49 side. As a result, the multiplier 47 multiplies the input signal by a coefficient of 1 and outputs the result.

A reference level generation circuit (REF) 45 supplies a predetermined reference level Lth (=L□) to the subtraction circuit 44. Therefore, the subtraction circuit 44 uses the absolute level Lin and the reference level Lth.
The difference (Lin-Lth=Δ) is output.

Since the multiplier 46 squares this difference, the multiplier 47 eventually outputs a value obtained by multiplying the square value of this difference by a coefficient of 1.

The output (k1Δ2) of this multiplier 47 is
8 to the addition/subtraction circuit 34. Therefore, the addition/subtraction circuit 34 subtracts the output of the multiplier 47 from the output of the attenuator 32 when the input signal xin is positive, and adds the latter to the former when the input signal xin is negative, and outputs the result. This output is the gain g
The signal is amplified by an amplifier 35 and outputted from a terminal 36.

That is, the output characteristic in this case is the region α (nonlinear region) in FIG. 4. As is clear from this characteristic diagram, the input signal is compressed or limited in this case.

FIG. 5 represents a second embodiment of the invention.

In this embodiment, the portion surrounded by broken lines in FIG. 1 is replaced with the configuration shown in FIG. 5.

In this embodiment, the multiplier 51 outputs the output (Δ
2) by the output (Δ) of the subtraction circuit 44, and the multiplier 5
2. The multiplier 52 outputs the output of the multiplier 51 (Δ
3), the coefficient output from the coefficient circuit 54 is multiplied by 2. The addition circuit 53 adds the output (Δ2) of the multiplier 46 and the output (k2Δ3) of the multiplier 52. Then, the multiplier 47 multiplies the output of the adder circuit 53 (Δ2+ by 2Δ3) by a coefficient kx (or k.). In this case, the complerus (limit) characteristic of the region α in FIG. 3 can be further enhanced than in the embodiment shown in FIG.

FIG. 6 shows a third embodiment. In this embodiment, in addition to the input terminal 31, another input terminal 61 is provided. A signal input from this input terminal 61 is input to an absolute value circuit 62, and its absolute value is detected.

A maximum value selection circuit (MAX SEL) 63 selects and outputs the larger of the outputs of the absolute value circuits 39 and 62. Other operations are similar to those in the embodiment shown in FIG.

The input terminals 31 and 61 in this embodiment are D in FIG.
They correspond to input terminals a1 and 82 in SP14L2.14R2, respectively.

In the case of this embodiment, even if the signal levels of the left and right channels are extremely different, the signal of one channel is prevented from being affected by the signal of the other channel and giving the impression of being clipped. be able to.

FIG. 7 shows a fourth embodiment. In this embodiment, the attenuator 33, comparator 40, and switch 41 in the embodiment of FIG.
FI) 71 and (REF2) 72, coefficient circuits 73 and 74 in place of the coefficient circuits 48 and 49, and comparators 77 and 78 in place of the comparator 42 are provided, respectively. Further, coefficient circuits 75 and 76 that generate the gain coefficient of the amplifier 35, and further these reference level generation circuits 71 and 72 and the coefficient circuit 73
A parameter memory 79 is provided for storing parameters such as levels and coefficients to be output to the output terminals 76 to 76. The other configurations are the same as in FIG. 1.

In this embodiment, predetermined parameters can be stored in the parameter memory 79 by operating the operating section 15 shown in FIG. The parameters stored in this parameter memory 79 are the reference level generation circuits 71 and 72.
, are transferred to coefficient circuits 73 to 76 and latched.

The absolute value level Lin output from the absolute value circuit 39 is compared with reference levels L11 and L2 (L□□<L1□) in comparators 77 and 78, respectively. When the absolute value level L, in is smaller than the reference level L, the comparator 77 activates the coefficient circuit 48 and sets the coefficient of the multiplier 47 to the value kfl (=O).

As a result, the addition/subtraction circuit 34 outputs the input signal that has been attenuated by the predetermined level by the attenuator 32 as is. As a result, the output characteristic of the addition/subtraction circuit 34 becomes the region β (linear region) in FIG. 8(a).

When the absolute value level Lin is larger than the reference level L11 and smaller than the reference level L, □2 (L□1≦Lin≦L
12), coefficient circuit 71.1 based on the output of comparator 77.
73 and 75 are activated. As a result, the subtraction circuit 44 outputs the absolute value level Lin and the reference level Lth, (=
The difference (Δ) with L11) is output, and the multiplier 47 outputs a value (k1Δ2) obtained by multiplying the square of this difference by a coefficient of 1. Since the difference between the output of the attenuator 32 and the output of the multiplier 47 is calculated in the addition/subtraction circuit 34, the output characteristics are as shown by the area α□ (first compressor or limiter area) in FIG. 8(a). Become. That is, the input signal is compressed or limited by some amount.

When the absolute value level Lin is greater than the reference level L02, the coefficient circuits 72, 74 and 76 are activated. As a result, the subtraction circuit 44 outputs the difference (Δ) between the absolute value level d, jn and the reference level ■, th, ("r-+□), and the multiplier 47 multiplies the square of this difference by a coefficient of 2. This coefficient is multiplied by 2 and output.Since 2 is set to a larger value, as shown in area α2 (second compressor or limiter area) in FIG. 34
The input signal is more strongly compressed or outputted to the limit 1 than in the region α.

The output of the adder/subtracter circuit 34 is multiplied by a predetermined gain coefficient by an amplifier 35. The gain coefficient in regions β and α is g
l, and the gain coefficient in region α2 is g2. coefficient g
□ is the amount of attenuation in the attenuator 32 (AT T)
It corresponds to -The force coefficient g2 is set to a value determined by the following equation.

g2=ATT2X(yc/Lth,) Here, the value yc is the output level of the addition/subtraction circuit 34 in the area α□ when the absolute value level Lin is equal to the reference level L1°. By setting the gain coefficients g1 and g2 in this manner, the characteristics of the output of the amplifier 35 can be set to continuous desired values, as shown in FIG. 8(b).

FIG. 9 shows a fifth embodiment. However, in this case, as shown in FIG. 10, the output data from the receiving section 12 is input as is to the input terminals a□ of the DSPs 14L2 and 14R2, and the data output from the previous stage DSP is input to the input terminal a2.
14. Output data from output terminals C of L□ and 14R□ are respectively input. In the case of this embodiment, the previous stage DSPL 4-L□ (14R□) serves as the delay circuit 81, and the subsequent stage DSPL 4-L□ (14R□) serves as the delay circuit 81.
R2) each operates as a processing circuit consisting of a rectifying and smoothing circuit 82, a loop filter 83, and processing sections 84 and 85.

For example, as shown in FIG. 11, the rectifying and smoothing circuit 82 includes an absolute value circuit 121, switches 122, 123, and 124 for selecting the larger of two inputs, and a predetermined coefficient Cc (0< Multiplier 12 that multiplies Cc<1)
5.126.127, a delay circuit (Ts) 128.129.130 that delays data by one sampling period, and multipliers 131 and 132 that multiplies the input signal by a predetermined coefficient (1-cc). It is composed of adder circuits 133 and 134.

Absolute value circuit 12] detects the absolute value of input signal xin,
Output. The detected absolute value level is provided to one input terminal of switch 122. Data selected by the switch 122 and delayed by one sampling period by the delay circuit 128 is input to the other input terminal of the switch 122 after being multiplied by a coefficient Cc by a multiplier 125 . Switch 122 selects the larger of the two inputs and outputs it. This selection output is the delay circuit 128
is again supplied to the other input terminal of the switch 122 via the multiplier 125, multiplied by a coefficient (1-Cc) by the multiplier 131, and then input to the addition circuit 133. .

The output of the switch 123 is also input to the adder circuit 133 via a delay circuit 129 and a multiplier 126.

The adder circuit 133 adds the two inputs and adds the two inputs to the switch 123.
is supplied to one input terminal of the The other input terminal of the switch 123 is supplied with the output of the absolute value circuit +21. Switch】23 selects the larger of the two inputs,
Output.

The output of switch 123 is connected to delay circuit 129 and multiplier 126.
The signal is supplied again to the adder circuit] 33 via the multiplier 132, and is also input to the adder circuit 134 via the multiplier 132. The output of the switch 124 is also input to the adder circuit 134 via a delay circuit 130 and a multiplier 127. Adder circuit 134 adds the two inputs and supplies the sum to one input terminal of switch 124. The output of the absolute value circuit 121 is supplied to the other input terminal of the switch 124, and the switch 124 selects the larger one of the two inputs and outputs it.

In this way, switches (122, 123, I24), delay circuits (128, 129, 130) and multipliers (125,
126, 127) are connected in cascade in three stages to form a rectifying and smoothing circuit.

In principle, one stage may be sufficient, but with one stage it is difficult to secure a sufficient release time, which will be described later.

The loop filter 83 is, for example, as shown in FIG.
A delay circuit that delays data by one sampling period (
Ts)91 to 96 and predetermined coefficients B(0), B(1), B(2), B1(O), Bl(1
), Bl(2), respectively, and outputs the multipliers 101 to 106, and input data is multiplied by a predetermined coefficient A(1).
, A(2), AI(1), and A 1 (2), and multipliers 107 to 109 that multiply and output the results, and adder circuits 111 and 112 that add input data.
Consists of filters.

The input data is transmitted through the multiplier 101, through the delay circuit 91 and the multiplier 102, and then through the delay circuit 91.
92 and a multiplier 103, they are each input to an adder circuit 111. The adder circuit 111 also has its output transmitted through a delay circuit 93 and a multiplier 107, and then to a delay circuit 93.
94 and a multiplier 108, respectively. Adder circuit 111 adds these inputs and outputs the result.

The output data of the adder circuit 111 is input to the adder circuit 112 via the multiplier 104, via the delay circuit 93 and the multiplier 105, and further via the delay circuits 93 and 94 and the multiplier 106. The adder circuit 112 also receives its output via a delay circuit 95 and a multiplier 109, and further via delay circuits 95 and 96 and a multiplier 109, respectively. Adder circuit 112 adds these inputs and outputs the result. In this way, the loop filter 83 is composed of two stages.

Furthermore, the processing units 84 and 85 are configured as shown in FIG. 13, for example.

In the processing unit 84, the difference (Δ) between the output of the loop filter 83 outputted by the subtraction circuit 44 and the reference level Lth is converted into a coefficient ka (for example, ka = 1/2) by the multiplier 141.
．． After being multiplied by 1/4, 1/8, . . . ), the signal is input to the adder circuit 142. The adder circuit 142 receives this input (ka
Δ) and the input (Δ2) from the multiplier 46 are added and supplied to the multiplier 47. Therefore, the multiplier 47 is the adder circuit 1
42 output (kaA+Δ2) with coefficient k. Or multiply by 1.

In the processing section 85 , the output of the delay circuit 81 is multiplied by a gain coefficient g by the amplifier 151 and then supplied to the addition/subtraction circuit 34 . The addition/subtraction circuit 34 outputs the difference between the output of the amplifier 151 and the output of the multiplier 147 to the overflow detection circuit 152. The overflow detection circuit 152 outputs the input signal as it is when the level is less than a predetermined value, and outputs a predetermined value when the level exceeds the predetermined value (overflow). In this way, output characteristics as shown in FIG. 14 are obtained.

When the input signal is a music signal, its level changes from moment to moment. Therefore, if the compressor or limiter characteristics are changed moment by moment in response to changes in the input level, the sound quality will be different from the original one. Therefore, it is preferable to keep the characteristics unchanged for a predetermined period of time.

In general, people are sensitive to changes in audio signals that suddenly increase in size, but are insensitive to changes in audio signals that suddenly decrease in size. Therefore, if the characteristics are always held constant for a predetermined period of time, an audio signal that suddenly increases will sound unnatural. It is preferable to keep the characteristics constant for a relatively long time against changes that decrease rapidly.

The loop filter 83 is a filter inserted into the feedforward loop system in order to set the attack time to a relatively short time in response to this sudden change in the size of one novel. This filter has the characteristic of differentiating signals in order to instantly detect sudden changes in signals.

As a result, from the rectifying and smoothing circuit 82, for example, as shown in FIG.
When a signal as shown in (b) of the same figure is inputted (the signal is represented in analog form for convenience), the output of the loop filter 83 becomes as shown in (b) of the same figure. In other words, the portion where the level suddenly increases becomes an emphasized signal. Coefficient k determined in processing section 84 corresponding to this partially emphasized signal. If the processing unit 85 performs signal processing according to parameters such as , and □, incorrect signal processing will be performed. Therefore, as shown in FIG. 15(c), the input signal is delayed by a predetermined time T by a delay circuit 81. This delay time T is set to a time sufficient for the partially emphasized waveform shown in FIG. 15(b) to disappear.

As a result, at the timing when the input signal is processed in the processing unit 85, the partially emphasized waveform disappears, and erroneous signal processing is prevented.

On the other hand, the rectifying and smoothing circuit 82 has a function of converting the input signal into DC to operate the loop filter 83, and a function of setting a relatively long release time in response to a sudden change in level. In other words, this circuit has the characteristic of integrating signals.

Therefore, the input signal as shown in FIG. 16(a) is
As shown in b), the signal is delayed by a predetermined time T by the delay circuit 81 and processed to have an attack time defined by the loop filter 83 and a release time defined by the rectification and smoothing circuit 82. Although the release time is also set by the loop filter 83, its value is small corresponding to the attack time, so the setting by the rectifying and smoothing circuit 82 is required. The rectifying and smoothing circuit 82 also sets an attack time, but since this time is sufficiently longer than the attack time of the loop filter 83, priority is given to the attack time of the loop filter 83.

FIG. 17 shows a sixth embodiment. In the case of this embodiment, in each DSP 14L2 and 14R2, a mixing circuit 162L,
162R is provided, and the left and right channel signals are mixed by this mixing circuit, and the average value of both is supplied to rectifying and smoothing circuits 82L and 82R, respectively. This embodiment is suitable when the level difference between the signals of both channels is small.

DSP14L2.14R2 is a mixing circuit 162L, 16
2R1 rectifier smoothing circuit 82L, 82R, loop filter 8
3L, 83R1 processing section 84L, 84R185L, 85R
etc. can be performed relatively quickly, and there is plenty of processing time. Therefore, delay circuits 161L and 161R are provided, and the DSP 14. Ll, 14R□ delay circuit 81L,
The delay time is set in combination with 81R.

〔Effect of the invention〕

As described above, according to the present invention, the function of the difference between the absolute value level of the input signal and the reference level is calculated, and the signal processing is performed in accordance with the calculation result, so that the digital signal can be processed accurately as it is. Not only is it possible to perform calculations, but it is not necessary to store a lot of data in a ROM table instead of performing calculations, and an inexpensive device can be realized.

In addition, if multiple parameters such as levels and coefficients necessary for calculations are stored in memory and the desired one can be selected, the same device can be used to generate expanders, compressors, limiters, etc. by simply switching the parameters. It becomes possible to perform multiple different functions. Furthermore, by simply changing the parameters for any level, it becomes possible to perform detailed and rapid processing with few errors.

Furthermore, when the rectifying and smoothing means and the filter means are used, it is possible to set desired attack and release times, and it is possible to prevent the occurrence of a "natural" aural sensation as a result of signal processing.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram of the DSP of the present invention, FIGS. 2 and 10 are block diagrams of the audio signal processing device of the present invention, FIG. 3 is a flowchart of the CPU of the present invention, and FIG. 4 is the same as that of the first embodiment. The input/output characteristic diagram of the device shown in FIG.
FIG. 6 is a functional block diagram of the third embodiment of the present invention, FIG. 7 is a functional block diagram of the fourth embodiment of the present invention, and FIG. 8 is a functional block diagram of the fourth embodiment of the present invention. An input/output characteristic diagram of the device, FIG. 9 is a functional block diagram of the fifth embodiment of the present invention,
FIG. 11 is a functional block diagram of the rectifying and smoothing circuit of the present invention, FIG. 12 is a functional block diagram of the loop filter of the present invention, FIG. 13 is a functional block diagram of the processing section of the present invention, and FIG. 14 is FIG. 15 and 16 are waveform diagrams explaining the operation of the loop filter and rectifying and smoothing circuit of the present invention, and FIG. 17 is a functional block diagram of the sixth embodiment of the present invention. be. 14 L,, 14 L2.14 R,, 14R2,,
, D S P, 32.33. ,,attenuator,37.
,,Polarity discrimination circuit, 39.62,121. ,,Absolute value circuit,40,42,77.78. ,, comparator, 45
, 71, 72. ,,Reference level generation circuit, 46.47
, 51, 52, 110 to 110, 141. ,,multiplier,48,49,73,74,75°76.125,12
6,127,131,132. ,,coefficient circuit,63. ,
. Maximum value selection circuit, 79. ,,parameter memory,81.
91 to 96.128, 129, 130. ,, delay circuit, 82°0. Rectifier smoothing circuit, 83. ,,Loop filter, 84°85,,,Processing unit, 152. ,,Overflow detection circuit. Patent applicant: Victor Japan Co., Ltd.

Claims (3)

[Claims] (1) Comparison means for comparing the level of the input signal with a predetermined reference level, and an operation for calculating a function regarding the difference between the level of the input signal and the reference level when the level of the input signal is higher than the reference level. means for determining the polarity of the input signal; addition and subtraction means for adding or subtracting the input signal and the output of the calculation means in accordance with the output of the determination means; A digital signal processing device comprising: multiplication means for multiplying by a predetermined gain coefficient. (2) comparing means for comparing the level of the input signal with a first reference level and a second reference level higher than the first reference level; and the level of the input signal is higher than the first reference level, and When the level of the input signal is smaller than the second reference level, the function regarding the difference between the level of the input signal and the first reference level is
calculation means for calculating a function related to the difference between the level of the input signal and the second reference level when the level of the input signal is greater than the reference level, a determining means for determining the polarity of the input signal, and an output of the determining means. an adding/subtracting means for adding or subtracting the input signal and the output of the arithmetic means, and when the level of the input signal is higher than the first reference level and lower than the second reference level, a multiplication means for multiplying the output of the addition/subtraction means by a first gain coefficient, and producing a second gain coefficient for the output of the addition/subtraction means when the level of the input signal is greater than the second reference level; Processing equipment. (3) rectifying means for rectifying an input signal and setting at least a release time of the input signal; a filter means for setting at least an attack time for the output of the rectifying means; a determining means for determining parameters for processing the input signal, a delay means for delaying the input signal for a predetermined time, and an output of the delay means,
and processing means for processing a signal corresponding to the output of the determining means.