JPH02277329A - Synchronizing circuit for random code for spreading spectrum - Google Patents

Abstract

PURPOSE:To quicken the establishment of synchronization by providing a shifter shifting a pseudo noise signal stored in advance. CONSTITUTION:A variable shift register 9 uses a reset signal Res generated at the same time as an input gate signal tw to decide a head code PN3 of a PN code generator 8, applies shift of bits to the code by a count output C of a counter 5 and outputs a pseudo random code PN4 synchronously with a spread input signal. An output of the variable shift register 9 is used to apply exclusive OR processing to the inputted spread signal with a spread demodulator 30, from which information data is outputted. Thus, the input spread signal is subject to inverse spread with an output of the variable shift register 9, and since the demodulated information data is coincident with the data of a sender and the pseudo random code PN4 being the synchronizing output is outputted directly from the variable shift register 9, much time is not required for generating an output.

Description

[Detailed Description of the Invention] [Summary] Regarding a synchronization circuit for spread spectrum random codes used in satellite communication lines, etc., for the purpose of shortening the time until synchronization is established, two periods of an input spread signal are written. A shift register is stored according to the input gate signal, and a pseudo-random code for one period in which one period's worth of spread signal, which is always included in the shift register, is stored in advance is shifted by the count output C of the counter using a shifter. A correlator that checks the number of matches between the output and the bit correspondence, and a spreading PN on the transmitting side that measures the number of matches between the codes of the output of the correlator.
Threshold value of “0” signal whose sign is not inverted (tolerance 0
) and the threshold of the inverted “1” signal (tolerance 4), if the number of matches from the correlator is greater than the threshold on the “0” side, or - when the political opponent is smaller than the threshold on the “1” side. a comparator that outputs an output as CLK; a latch that captures the counting output C of the counter with the output CLK of the comparator; and a PN code generator that is cued by a reset signal generated simultaneously with the input gate signal; One cycle of PN from the PN code generator is controlled by the output of the latch.
A variable shift register for shifting the code is provided, and the variable shift register shifts the PN code for one period from the PN code generator by the count output C of the counter for despreading synchronized with the input spread signal. It is configured to output a PN code of .

[Industrial application field]

The present invention relates to a circuit for receiving and demodulating a spread spectrum signal code-processed with a pseudo-random code on a transmitting side used in a satellite communication line etc., and particularly for demodulating a received spread spectrum signal 5S for demodulating a direct spread signal. - Regarding the synchronization circuit for PN.

[Conventional technology]

In the direct spread method of spread spectrum communication, the bit rate R1 of the transmitted data is modulated on the transmitting side.
EX with the output of the r'N code generator that generates a pseudorandom code PN at a rate Rc that is a multiple (a fairly large multiple) of
-5equence I whose sign is inverted by OR processing
SS (Sp
readSpectrum ) signal, and on the receiving side, the received 5S-PN signal is subjected to EXOR processing with the output of a PN code generator with a rate Rc that is in phase with the PN code on the transmitting side, that is, synchronized, to convert the original information data. Despread demodulation is performed, but conventional synchronization with the received signal of the PN code generator on the receiving side is performed using the DLL (Delay) shown in Fig. 3.
As shown in the LockedLoop) type synchronous circuit, a spread spectrum signal 5S-PNin received from the transmitting side is input, first branched into two by a hybrid 18, and each branched signal is sent to a multiplier 21A1 and a multiplier 2□. , the outputs to the gate sequence generator 6 which generate gate sequence codes which are noisy but deterministic periodic sequences, which differ by one clock from each other, are multiplied by D, and the input signals 5S-PNin and The phase difference φ1. Outputs voltage V, V2 according to φ2.

Then, the difference between the two voltages V,, V, is taken by the differentiator 48,
A voltage C obtained by integrating the voltage V of the difference by a loop filter 3A is used as a control voltage to control the oscillation frequency of a voltage controlled oscillator (VCO) 5A. Then, the sequence generator 6A is driven by the output signal of the voltage controlled oscillator 5A to form an analog phase locked loop PLL. Then, the PLL controls the voltage controlled oscillator 58 so that the difference voltage V between the output voltages V and V2 to the difference generator 4 becomes zero, and the outputs D+ and Dz of the gate sequence generator 6A become the human input signal 5S-PNin. to synchronize with. Then, the output D2 of the H sequence generator 6A is converted to the length of 1 bit in the H sequence, that is, the clock length Δ
The received signal 5S is delayed by a half of Δ/2.
- The spreading demodulator IOA that performs EX-OR processing on PNin correctly demodulates and restores the original information data.

[Problem to be solved by the invention]

The conventional synchronization circuit for random codes for spread spectrum is
As described above, an analog phase-locked loop PLL is formed, and the output of the H-sequence generator 6A of the loop PLL,
Since D2 is synchronized with the received input signal 5S-PNin, there is a drawback that it takes too much time to establish synchronization by the PLL loop. The present invention is based on this same MV.
The object of the present invention is to provide a synchronization circuit for a spread spectrum random code that shortens the time required for one signal to rise.

[Means to solve the problem]

This problem is solved because the pseudorandom code PN that creates the spread spectrum signal 5SPN generally uses one sequence.
If even one bit is out of phase between two PN codes, the number of matches between the codes will be halved to 50%, and
“0” of information data whose sign is not inverted by the PN code
If the number of matches between the two PN codes of the “1” signal is 100%, the number of matches between the two PN codes of the inverted “1” signal is 0.
%, as shown in FIG. 1, two periods of the received human-powered diffusion signal 5s-pN are stored in the shift register 1 using the write input gate signal t1 generated by the control unit 10. , 1 that is always in the shift register
The correlator 2 generates a shift output PN2 by bit-shifting the pseudo noise code PN for one period stored in the memory 3 by the count output C of the counter 5 using the shifter 4 for the 5S-PNI for the period. Find the number of bitwise matches.

Then, the number of matching signs of the output of the correlator 2 is determined by the comparator 6 as the threshold value (tolerance 0) of the "0" signal that does not invert the original information data among the input 5S-PN, and the original information data. is compared with the threshold of the inverted "l" signal (tolerance 4), and if the number of matches from correlator 2 is larger than the threshold on the "0" side (tolerance 0), or the political opponent If the tolerance is smaller than tolerance 4), an output CLK is output, the count output C of the counter 5 is taken into the latch 7 by the output CLK, the variable shift register 9 is controlled by the output of the launch 7, and the variable shift register 9 is At, P.N.
The input gate signal 1. from the code generator 8 is input to the control unit 10. The PNN code N3 for one period, which was started by the reset signal Res generated at the same time, is shifted by the count output C of the counter 5, and the variable shift register 9 generates a PNN code N4 for despreading that is phase-synchronized with the input signal 5Sin. This problem is solved by the present invention, which outputs the following.

In the principle diagram of FIG. 1 showing the basic configuration of a synchronization circuit for a spread spectrum random code according to the present invention, reference numeral 1 indicates a write input for two cycles of an input spread signal 5S-PN generated by a control unit 10. Gate signal t. This is a shift register that stores data.

2 is 5 for one cycle, which is always included in shift register 1.
A shift output PN2 is obtained by bit-shifting the pseudo-random code PN for one period stored in the memory 3 in advance by the count output C of the counter 5 with respect to S-PN by the shifter 4.
This is a correlator that checks the number of matches between codes corresponding to bits and bits.

3 is a correlator 2 which stores in advance a pseudo-noise code PN for one period, which is a reference for checking the number of matches of bit-corresponding codes, with respect to one period of 5S-PNI from the shift register 1. It's memory.

4 is a shifter which outputs a shift output PN2 which is bit-shifted by the count output C of the counter 5 with respect to the reference pseudo-noise code PN for one period stored in advance in the memory 3.

5 is a counter that counts the clock time during which the shifter 4 has shifted bits and outputs a count output C.

6 is the number of sign coincidences of the output of the correlator 2, the threshold of the "0" signal (tolerance 0) of the 5S-PN of the input of the correlator 2, which did not invert the original information data on the transmitting side, and ,
The original information data is compared with the threshold of the inverted "1" signal (tolerance 4), and if the number of matches from the correlator 2 is greater than the threshold of the "0" side (tolerance 0), - the political opponent is "l"
” side threshold (tolerance 4), the output CL
This is a comparator that outputs K.

Reference numeral 7 denotes a latch which takes in the counting output C of the counter 5 using the output CLK of the comparator 6, and uses the output to set the variable shift register 8 to Ill<.

8 is the input gate signal 1.8 in the control section 10. This is a PN code generator that is reset by a reset signal Res generated at the same time as 1, cues the first code PN31, and outputs a pseudorandom code PN3.

Reference numeral 9 denotes a variable shift register which is controlled by the output of the latch 7 and which bit-shifts the pseudo-random code PN3 for one period from the N code generator 8 by the count output C of the counter 5 and outputs the result.

10 generates the input gate signal t, 1 for writing the manual signal 5S-PNI into the shift register 1, and at the same time outputs the PN signal.
This is a control unit that generates a reset signal Res that determines the cue position of the output PN3 of the code generator 9.

[Effect]

The control unit 10 of the present invention receives an input gate signal t. The set signal Res is simultaneously generated, the input gate signal t9 is supplied to the shift register 1, two periods of the input spread signal 5S-PN are stored in the shift register 1, and the reset signal R is generated.
es is supplied to the PN code generator 9 to reset it, and the cue of the output PN3 of the PN code generator 9 is determined.

The correlator 2 uses the shifter 4 to count and output the pseudo noise code PN for one period, which is stored in the memory 3 in advance, for the 5S-PNI for one period, which is always stored in the shift register 1, from the counter 5. Shifted output PN bit-shifted by C
2 and the bit-corresponding code are checked, and the number of matches between the codes is outputted to the comparator 6.

The comparator 6 calculates the number of sign coincidences of the output of the correlator 2 by comparing the signal tolerance of the manually generated 5S-PN of the correlator 2 that did not invert the original information data on the transmitting side. 0) and the threshold value of the “l′” signal (
Tolerance 1), the number of matches from correlator 2 is “0”.
The output CLK is outputted and supplied to the latch 7 when it is larger than the threshold on the ``1'' side (tolerance 0) or when the - political opponent is smaller than the threshold on the ``1'' side (tolerance 1).

The latch 7 connects the counter 5 with the output C1, K of the comparator 6.
The variable shift register 9 is controlled by the output. The variable shift register 9 is controlled by the output of the latch 7, and determines the leading code PN31 of the output PN3 of the PN code generator 8 by the reset signal Res generated at the same time as the input gate signal tw in the control unit 10. PNN code N for one period from 8
3 by bit-shifting by the count output C of counter 5,
Pseudo-random code P synchronized with input spread signal 5SPN
N4 is output and used for despreading the input spread signal 5S-PN.

Therefore, the spread spectrum random code synchronization circuit of the present invention has the output code PN of the variable shift register 9,
The input spread signal 5S-PN @EX-OR processed and despread demodulated information data correctly matches the original information data on the transmitting side, and the output code PN4 is as in the conventional example.
Since it is output from the variable shift register 9 without using a PLL loop, the input spread signal SS-PN for despreading
The conventional problem is solved because it does not take much time to obtain a PN code synchronized with the PN code.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a synchronization circuit for a spread spectrum random code according to an embodiment of the present invention, and is an embodiment in which the synchronization circuit is provided with forward/backward protection.

In FIG. 2, circuits that are the same as in FIG. 1 use the same symbol numbers.

Newly installed front/rear protection circuit 20 in Figure 2
is a well-known technique, and after detecting and confirming that the output CLK of the comparator 6 is input a predetermined number of times under the predetermined forward condition and backward condition, the output CLK whose protection has been confirmed is sent to the latch 7.
is supplied to the D flip-flop D-FF. Then, the D-FF of the latch 7 takes in the count output C of the counter 5 using the output CLK of the comparator 6 which is confirmed and protected by the forward/backward protection circuit 20, and uses the output of the D-FF to input the variable shift register 9. Control. The variable shift register 9 is controlled by the output of the D-FF of the latch 7, and the control unit 1
0, input gate signal 1. The leading code PN31 of the output PN3 of the PN code generator 8 is determined by the reset signal Res generated at the same time, and the P for one period from the PN code generator 8 is determined.
The NN code N3 is bit-shifted by the count output C of the counter 5, and a pseudorandom code PN4 synchronized with the input spread signal 5S-PN is output. Then, using the pseudo-random code PNA output from the variable shift register 9, the spread demodulator 30 converts the input spread signal 5S-PN into F,X-
Performs 0R processing and outputs information data.

Therefore, the spread spectrum random code synchronization circuit of the embodiment shown in FIG.
The information data obtained by despreading N and demodulating it correctly matches the original information data on the transmitting side, and the pseudo random code PN of the synchronized output is different from the conventional example without using a PLL loop. , shift register 1. Correlator 2. Counter 5. Comparator 6. Since the signal is directly output from the register 9 to the variable shift 1 using a one-way circuit such as the latch 7 and the PN code generator 8, there is no problem since it does not take much time to form the output.

〔Effect of the invention〕

As explained below (1), according to the present invention, the despreading PN synchronized with the received spread spectrum signal SS-PN
Since it does not take much time to form the code output, if it is applied to a satellite link, if multiple earth stations randomly access and use the satellite station, each time a call is made to each earth station, the Since the code synchronization for performing spread demodulation of reception can be completed in a short time, the operational efficiency of the satellite link can be improved.

[Brief explanation of drawings]

FIG. 1 is a principle diagram showing the basic configuration of a synchronization circuit for a spread spectrum random code according to the present invention, FIG. 2 is a block diagram showing the configuration of a synchronization circuit for a spread spectrum random code according to an embodiment of the present invention, and FIG. The figure is a block diagram of a conventional DDL type synchronous circuit. In the figure, 1 is a shift register, 2 is a correlator, 3 is a memory, 4 is a shifter, 5 is a counter, 6 is a comparator, 7 is a latch, and 8 is a P
N code generator, 9 is variable shift register, 10 is control '4
? Parts 11 and 20 are front/rear protection circuits.

Claims (1)

[Claims] Information data is code-processed using a pseudo-random PN code on the transmitting side, and the PN code is not inverted, which is a “0” signal, and an inverted “0” signal.
A spread spectrum signal (SS-
PN) and outputs a despreading PN code (PN_4) synchronized with the received signal, two periods of the input spread signal are input to the write input generated by the control unit (10). The shift register (1) to be stored by the gate signal (t_w) and the spread signal (SS-PN_1) for one period, which is always included in the shift register, are stored in advance in the memory (
3) Pseudo-random code (PN
_0) by the shifter (4) and the counting output C of the counter (5)
A correlator (2) that checks the number of matches between the bit correspondence and the output (PN_2) shifted by 1, and the number of matches of the sign of the output of the correlator is inverted by inverting the information data of the input spread signal (SS-PN_1). Compare the threshold value (tolerance_0) of the "0" signal that did not occur and the threshold value (tolerance_1) of the "1" signal obtained by inverting the information data, and determine the threshold value (tolerance_0) at which the number of matches from the correlator is on the "0" side. ) or when the number of matches is smaller than a threshold value (tolerance_1) on the “1” side, a comparator (6) outputs an output (CLK);
The output sign is determined by a latch (7) that captures the count output C of the counter (5) using the output CLK of the comparator, and a reset signal (Res) generated simultaneously with the input gate signal (t_w) by the control unit (10). a PN code generator (8) in which the PN code is cued, and a variable shift register (9) that is controlled by the output of the latch and shifts one cycle of the PN code (PN_3) from the PN code generator; The variable shift register (9) transfers one period of the PN code (PN_3) from the PN code generator (8) to the counter (
5) is shifted by the count output C, and the input spread signal (SS
- A random code synchronization circuit for spread spectrum use, characterized in that it outputs a PN code (PN_4) for despreading synchronized with PN).