JPH02277347A - Two-way bus test circuit - Google Patents

Two-way bus test circuit

Info

Publication number
JPH02277347A
JPH02277347A JP1099504A JP9950489A JPH02277347A JP H02277347 A JPH02277347 A JP H02277347A JP 1099504 A JP1099504 A JP 1099504A JP 9950489 A JP9950489 A JP 9950489A JP H02277347 A JPH02277347 A JP H02277347A
Authority
JP
Japan
Prior art keywords
test
bidirectional
bus
lsi
direction control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1099504A
Other languages
Japanese (ja)
Inventor
Hideyuki Kori
郡 秀之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1099504A priority Critical patent/JPH02277347A/en
Publication of JPH02277347A publication Critical patent/JPH02277347A/en
Pending legal-status Critical Current

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  • Maintenance And Management Of Digital Transmission (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To conduct the test of a 2-way bus without operating an internal circuit of an LSI by disconnecting the 2-way bus from the internal circuit when a test signal is received and connecting the 2-way bus to a 2-way test bus gate section. CONSTITUTION:Internal circuit disconnecting sections 3a-3c receive a test start signal via a test terminal 6a to disconnect an LSI internal circuit 8 from 2-way buses 9a-9c. Then a direction control section 2a receives a direction switching signal via a test terminal 6b and sends the signal to direction control sections 2b, 2c. The direction control sections 2b, 2c receive the signal to switch the destination of the signal to apply direction control of gate sections 10a-10f connecting to the 2-way buses 9a-9c from a conventional LSI circuit 8 to the direction control section 2a. Thus, the LSI circuit 8 is disconnected at the test.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、双方向バスを有するLSIを容易に試験を行
う双方向バス試験回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bidirectional bus test circuit that easily tests an LSI having a bidirectional bus.

〔従来の技術〕[Conventional technology]

論理回路の高集積化が進むにつれて、その試験はますま
す難しくなってきている。従来、LSIの順序回路に対
する試験容易化技法として、試験時には回路中のフリッ
プフロップをシフトレジスタとして動作させ、テストベ
クトルの設定と、1クロツクだけ通常動作させた後の状
態ベクトルの取出しを行うスキャンバス方式が実用化さ
れている。通常、双方向バスを有するLSIは、この方
法により試験されている。
As logic circuits become more highly integrated, their testing becomes increasingly difficult. Conventionally, as a test facilitation technique for LSI sequential circuits, a scan scan method has been used that operates a flip-flop in the circuit as a shift register during testing, sets a test vector, and extracts a state vector after normal operation for one clock. The method has been put into practical use. Usually, LSIs having bidirectional buses are tested using this method.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のスキャンパス方式では、主としてLSI
の内部回路の試験に主眼がおかれているため、LSIが
搭載されている電子回路パネル及び電子回路パネル相互
間の接続を主体にチエツクしたい場合には、この方法は
適切な方法とはいえない。特に、双方向バスを有するL
SIが搭載されている電子回路パネル及び電子回路パネ
ル相互間の接続試験を行うときには、双方向バスを制御
するためにLSIの内部回路を動作させる試験データを
作成する必要がある。そのため多大な工数と高い技術レ
ベルが要求されるという欠点がある。
In the conventional scan path method mentioned above, mainly LSI
Since the main focus is on testing the internal circuits of the LSI, this method is not appropriate if you want to mainly check the electronic circuit panels on which the LSI is mounted and the connections between the electronic circuit panels. . In particular, L with a bidirectional bus
When performing a connection test between an electronic circuit panel on which an SI is mounted and the electronic circuit panels, it is necessary to create test data for operating the internal circuits of the LSI in order to control the bidirectional bus. Therefore, it has the drawback of requiring a large amount of man-hours and a high technical level.

本発明の目的は、双方向バスを有するLSIを搭載した
電子回路パネルの試験を行うとき、LSIの内部回路を
動作させることなく双方向バスを試験することができる
双方向バス試験回路を提供することにある。
An object of the present invention is to provide a bidirectional bus test circuit that can test an electronic circuit panel equipped with an LSI having a bidirectional bus without operating the internal circuits of the LSI. There is a particular thing.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の双方向バス試験回路は、双方向バス及びLSI
を機能させる内部回路を持つLSIに設けられた双方向
バス試験回路において、切替信号を受信しデータ転送の
方向を制御する方向制御部と、前記方向制御部の制御に
よりゲートの開閉を行う双方向試験バスゲート部と、試
験信号を受信し前記双方向バスを前記内部回路から切離
す切離し部と、切離された双方向バス相互間に前記双方
向試験バスゲート部を介して接続された双方向試験ハス
とを備えて構成されている。
The bidirectional bus test circuit of the present invention is suitable for bidirectional buses and LSI
In a bidirectional bus test circuit installed in an LSI that has an internal circuit that functions, there is a direction control section that receives a switching signal and controls the direction of data transfer, and a bidirectional bus that opens and closes a gate under the control of the direction control section. a test bus gate section; a disconnection section that receives a test signal and disconnects the bidirectional bus from the internal circuit; and two devices connected between the separated bidirectional buses via the bidirectional test bus gate section. It is configured with a test lotus for the test.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例によるLSIのブロック図で
ある。
FIG. 1 is a block diagram of an LSI according to an embodiment of the present invention.

第1図に示したLSIIは、双方向バス端子7a〜7c
と、LSIを機能させるLSI内部回路8と、双方向バ
ス9a〜9Cと、双方向バス9a〜9Cに接続されたゲ
ート部10a〜10fとに加え、新たに切替信号を受信
しデータ転送の方向を制御する方向制御部2a〜2Cと
、方向制御部2a〜2Cの制御によりゲートの開閉を行
う双方向試験バスゲート部5a〜5fと、試験信号を受
信し双方向バス9a〜9CをLSI内部回路8から切離
す切離し部3a〜3Cと、切離された双方向バス相互間
に双方向試験バスゲート部5a〜5fを介して接続され
た双方向試験バス4と、試験情報信号を中継接続する試
験端子6a6bとを有している。
The LSII shown in FIG. 1 has bidirectional bus terminals 7a to 7c.
In addition to the LSI internal circuit 8 that makes the LSI function, the bidirectional buses 9a to 9C, and the gate sections 10a to 10f connected to the bidirectional buses 9a to 9C, the LSI receives a new switching signal and determines the direction of data transfer. direction control units 2a to 2C, which control the direction control units 2a to 2C, bidirectional test bus gate units 5a to 5f, which open and close gates under the control of the direction control units 2a to 2C, and bidirectional test bus gate units 5a to 5f, which receive test signals and control the bidirectional buses 9a to 9C inside the LSI. The test information signal is relay-connected to the disconnection sections 3a to 3C disconnected from the circuit 8 and the bidirectional test bus 4 connected between the disconnected bidirectional buses via the bidirectional test bus gate sections 5a to 5f. It has test terminals 6a6b.

双方向バス端子7a〜7c、試験端子6b、双方向試験
バス4は、通常それぞれ複数設けられているが、本例で
は1つのみが示されている。
Although a plurality of bidirectional bus terminals 7a to 7c, test terminals 6b, and bidirectional test bus 4 are normally provided, only one is shown in this example.

双方向バス9a〜9cを有するLSIIの試験は次の通
り行う。
Testing of an LSII having bidirectional buses 9a to 9c is performed as follows.

始めに、内部回路切離し部3a〜3Cは、試験端子6a
を介して試験開始信号を受信し、LSI内部回路8を双
方向バス9a〜9Cから切離す。
First, the internal circuit disconnection parts 3a to 3C are connected to the test terminal 6a.
A test start signal is received via the LSI internal circuit 8, and the LSI internal circuit 8 is disconnected from the bidirectional buses 9a to 9C.

次に、方向制御部2aは、試験端子6bを介し方向切替
信号を受信し、双方向試験バスゲート部5a〜5fの方
向制御を行うと共にこの信号を方向制御部2b、2cへ
伝達する。方向制御部2b、2cは、試験開始信号を受
信することにより、双方向バス9a〜9cに接続された
ゲート部10a〜10fの方向制御をするための信号の
受信先を通常のLSI内部回路8から方向制御部2aか
らに切替える。このようにしてLSI内部回路8を動作
させることなく、双方向バス9a〜9cを双方向試験バ
ス4を経由して相互に接続させて、双方向バス端子7a
〜7c間でデータの送受を行わせる。
Next, the direction control section 2a receives the direction switching signal via the test terminal 6b, controls the direction of the bidirectional test bus gate sections 5a to 5f, and transmits this signal to the direction control sections 2b and 2c. By receiving the test start signal, the direction control units 2b and 2c change the reception destination of the signal for controlling the direction of the gate units 10a to 10f connected to the bidirectional buses 9a to 9c to the normal LSI internal circuit 8. The direction control unit 2a is switched from the direction control unit 2a to the direction control unit 2a. In this way, the bidirectional buses 9a to 9c are connected to each other via the bidirectional test bus 4 without operating the LSI internal circuit 8, and the bidirectional bus terminal 7a is connected to the bidirectional bus terminal 7a.
Data is sent and received between 7c and 7c.

従って、同一電子回路パネル内の双方向バスを有するL
SIを搭載した他のLSIにもこの方法を適用して、L
SIの内部回路を動作させることなく、双方向バスを試
験することができ、電子回路パネル相互間の接続試験を
行うことができる。
Therefore, L with bidirectional buses within the same electronic circuit panel
Applying this method to other LSIs equipped with SI, L
A bidirectional bus can be tested without operating the internal circuits of the SI, and connections between electronic circuit panels can be tested.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、双方向バスを有するL
SIを搭載した電子回路パネルの試験を行うとき、LS
Iの内部回路を動作させることなく容易に双方向バスを
試験することが可能となるため、LSI本来の機能動作
を充分に理解できるような高度の技術レベルを不要とし
、かつ電子回路パネルの試験データを作成する工数を大
幅に削減することができる効果を有する。
As explained above, the present invention provides L
When testing electronic circuit panels equipped with SI, LS
Since it is possible to easily test the bidirectional bus without operating the internal circuit of the IC, it is not necessary to have a high technical level to fully understand the original functional operation of the LSI, and it is also possible to test the electronic circuit panel. This has the effect of significantly reducing the number of man-hours required to create data.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例によるLSIのブロック図で
ある。 1・・・・・・LSI、2a〜2C・・・・・・方向制
御部、3a〜3C・・・・・・切離し部、4・・・・・
・双方向試験バス、5a〜5f・・・・・・双方向試験
バスケート部、6a、6b・・・試験端子、7a〜7c
・・・・双方向バス端子、8・・・・・・LSI内部回
路、9a〜9c・・・・・・双方向バス、10a〜10
f・・・・・・ゲート部。
FIG. 1 is a block diagram of an LSI according to an embodiment of the present invention. 1... LSI, 2a to 2C... Direction control section, 3a to 3C... Separation section, 4...
・Bidirectional test bus, 5a to 5f...Bidirectional test bus skate section, 6a, 6b...Test terminal, 7a to 7c
...Bidirectional bus terminal, 8...LSI internal circuit, 9a-9c...Bidirectional bus, 10a-10
f...Gate part.

Claims (1)

【特許請求の範囲】[Claims] 双方向バス及びLSIを機能させる内部回路を持つLS
Iに設けられた双方向バス試験回路において、切替信号
を受信しデータ転送の方向を制御する方向制御部と、前
記方向制御部の制御によりゲートの開閉を行う双方向試
験バスゲート部と、試験信号を受信し前記双方向バスを
前記内部回路から切離す切離し部と、切離された双方向
バス相互間に前記双方向試験バスゲート部を介して接続
された双方向試験バスとを備えたことを特徴とする双方
向バス試験回路。
LS with bidirectional bus and internal circuit to function LSI
In the bidirectional bus test circuit provided in I, a direction control section receives a switching signal and controls the direction of data transfer, a bidirectional test bus gate section opens and closes a gate under control of the direction control section, and a test A disconnection unit that receives a signal and disconnects the bidirectional bus from the internal circuit, and a bidirectional test bus connected between the disconnected bidirectional buses via the bidirectional test bus gate unit. A bidirectional bus test circuit characterized by:
JP1099504A 1989-04-18 1989-04-18 Two-way bus test circuit Pending JPH02277347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1099504A JPH02277347A (en) 1989-04-18 1989-04-18 Two-way bus test circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1099504A JPH02277347A (en) 1989-04-18 1989-04-18 Two-way bus test circuit

Publications (1)

Publication Number Publication Date
JPH02277347A true JPH02277347A (en) 1990-11-13

Family

ID=14249099

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1099504A Pending JPH02277347A (en) 1989-04-18 1989-04-18 Two-way bus test circuit

Country Status (1)

Country Link
JP (1) JPH02277347A (en)

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