JPH0227741U - - Google Patents
Info
- Publication number
- JPH0227741U JPH0227741U JP10600988U JP10600988U JPH0227741U JP H0227741 U JPH0227741 U JP H0227741U JP 10600988 U JP10600988 U JP 10600988U JP 10600988 U JP10600988 U JP 10600988U JP H0227741 U JPH0227741 U JP H0227741U
- Authority
- JP
- Japan
- Prior art keywords
- signal pins
- output
- signal
- output circuit
- distributed manner
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図乃至第４図はこの考案の第１の実施例乃
至第４の実施例に係る集積回路のピン配置構造を
示す図である。
Ａ０〜Ａ７……アドレス信号ピン、Ｄ０〜Ｄ７
……データ信号ピン、Ｂ０〜Ｂ９，Ｃ０〜Ｃ５，
Ｅ０〜Ｅ５……同一機能信号ピン。
1 to 4 are diagrams showing pin arrangement structures of integrated circuits according to first to fourth embodiments of this invention. A0~A7...Address signal pin, D0~D7
...Data signal pins, B0 to B9, C0 to C5,
E0 to E5... Same function signal pins.
Claims (1)
からなる情報のそれぞれのビツト信号を外部へ出
力する複数の信号ピンを備え、前記複数の信号ピ
ンに対応したそれぞれの出力回路が分散されて配
置されるように、前記複数の信号ピンを分散して
配置したことを特徴とする集積回路のピン配置構
造。 (2) 出力回路から与えられる複数のビツト信号
からなる情報のそれぞれのビツト信号を外部へ出
力する複数の信号ピンの組を少なくとも２組備え
、前記複数の信号ピンに対応したそれぞれの出力
回路が分散されて配置されるように、それぞれの
組の信号ピンを混在させてそれぞれの組の複数の
信号ピンを分散して配置したことを特徴とする集
積回路のピン配置構造。 (3) 出力回路から与えられる複数のビツト信号
からなる情報のそれぞれのビツト信号を外部へ出
力する複数の信号ピンの組を少なくとも２組備え
、前記複数の信号ピンに対応したそれぞれの出力
回路が分散されて配置されるように、それぞれの
組の信号ピンを交互に配置して分散したことを特
徴とする集積回路のピン配置構造。 (4) 前記複数の信号ピンに対応した出力回路は
、異なる電源系統から電源の供給を受けることを
特徴とする請求項１乃至請求項３に記載の集積回
路のピン配置構造。 (5) 出力回路から与えられるアドレス信号を外
部へ出力する複数のアドレス信号ピンと、出力回
路から与えられるデータ信号を外部へ出力する複
数のデータ信号ピンを備え、それぞれの信号ピン
に対応した出力回路が分散されて配置されるよう
に、前記両信号ピンを分散して配置したことを特
徴とする集積回路のピン配置構造。 (6) 出力回路から与えられるアドレス信号を外
部へ出力する複数のアドレス信号ピンと、出力回
路から与えられるデータ信号を外部へ出力する複
数のデータ信号ピンを備え、それぞれの信号ピン
に対応した出力回路が分散されて配置されるよう
に、前記両信号ピンの少なくとも一部の信号ピン
を交互に配置して分散したことを特徴とする集積
回路のピン配置構造。 (7) 前記アドレス信号ピンとデータ信号ピンに
対応した出力回路は、異なる電源系統から電源の
供給を受けることを特徴とする請求項５及び請求
項６記載の集積回路のピン配置構造。 (8) 前記アドレス信号ピンの一部とデータ信号
ピンの一部にそれぞれ対応した出力回路は、同一
の電源系統から電源の供給を受けることを特徴と
する請求項５及び請求項６に記載の集積回路のピ
ン配置構造。[Claims for Utility Model Registration] (1) A device is equipped with a plurality of signal pins for outputting each bit signal of information consisting of a plurality of bit signals given from an output circuit to the outside, and has a plurality of signal pins corresponding to the plurality of signal pins. A pin arrangement structure for an integrated circuit, characterized in that the plurality of signal pins are arranged in a distributed manner so that output circuits are arranged in a distributed manner. (2) At least two sets of a plurality of signal pins are provided for outputting each bit signal of information consisting of a plurality of bit signals given from an output circuit to the outside, and each output circuit corresponding to the plurality of signal pins is provided. A pin arrangement structure for an integrated circuit characterized in that signal pins of each group are mixed and a plurality of signal pins of each group are arranged in a distributed manner so as to be arranged in a distributed manner. (3) At least two sets of a plurality of signal pins are provided for outputting each bit signal of information consisting of a plurality of bit signals given from an output circuit to the outside, and each output circuit corresponding to the plurality of signal pins is provided. A pin arrangement structure for an integrated circuit characterized in that each set of signal pins is alternately arranged and distributed so that the signal pins are arranged in a distributed manner. (4) The pin arrangement structure of an integrated circuit according to claim 1, wherein the output circuits corresponding to the plurality of signal pins receive power from different power supply systems. (5) An output circuit that is equipped with multiple address signal pins that output address signals given from the output circuit to the outside, and multiple data signal pins that output data signals given from the output circuit to the outside, and that corresponds to each signal pin. A pin arrangement structure for an integrated circuit, characterized in that both the signal pins are arranged in a distributed manner so that the signal pins are arranged in a distributed manner. (6) An output circuit that is equipped with multiple address signal pins that output address signals given from the output circuit to the outside, and multiple data signal pins that output data signals given from the output circuit to the outside, and that corresponds to each signal pin. A pin arrangement structure for an integrated circuit, characterized in that at least some of the signal pins are alternately arranged and distributed so that the signal pins are arranged in a distributed manner. (7) The pin arrangement structure of an integrated circuit according to claim 5 or claim 6, wherein the output circuits corresponding to the address signal pin and the data signal pin receive power from different power supply systems. (8) The output circuits according to claims 5 and 6, wherein the output circuits respectively corresponding to a portion of the address signal pins and a portion of the data signal pins receive power from the same power supply system. Integrated circuit pinout structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988106009U JPH0749803Y2 (en) | 1988-08-12 | 1988-08-12 | Pin layout structure of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988106009U JPH0749803Y2 (en) | 1988-08-12 | 1988-08-12 | Pin layout structure of integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0227741U true JPH0227741U (en) | 1990-02-22 |
| JPH0749803Y2 JPH0749803Y2 (en) | 1995-11-13 |
Family
ID=31339139
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988106009U Expired - Lifetime JPH0749803Y2 (en) | 1988-08-12 | 1988-08-12 | Pin layout structure of integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0749803Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6390865U (en) * | 1986-12-04 | 1988-06-13 |
-
1988
- 1988-08-12 JP JP1988106009U patent/JPH0749803Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6390865U (en) * | 1986-12-04 | 1988-06-13 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0749803Y2 (en) | 1995-11-13 |
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