JPH044432U - - Google Patents
Info
- Publication number
- JPH044432U JPH044432U JP4531890U JP4531890U JPH044432U JP H044432 U JPH044432 U JP H044432U JP 4531890 U JP4531890 U JP 4531890U JP 4531890 U JP4531890 U JP 4531890U JP H044432 U JPH044432 U JP H044432U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- flop
- integrated circuit
- semiconductor integrated
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
Description
第１図は本考案の第一実施例の要部を示す回路
図。第２図は本考案の第二実施例の要部を示す回
路図。第３図は本考案の第三実施例の要部を示す
回路図。第４図は従来例の要部を示す回路図。
１１……初段クロツクドライバＤ１、１２……
次段クロツクドライバＤ２、１３……終段クロツ
クドライバＤ３、１４……フリツプフロツプＦＦ
、２０〜２９……クロツクドライバＤ、Ｃ……ク
ロツク信号、Ｌ１〜Ｌ３，Ｌ１ａ〜Ｌ３ａ……配
線。
FIG. 1 is a circuit diagram showing the main parts of a first embodiment of the present invention. FIG. 2 is a circuit diagram showing the main parts of a second embodiment of the present invention. FIG. 3 is a circuit diagram showing the main parts of a third embodiment of the present invention. FIG. 4 is a circuit diagram showing the main parts of a conventional example. 11...First stage clock driver D1 , 12...
Next-stage clock driver D2 , 13...Last-stage clock driver D3 , 14...Flip-flop FF
, 20-29...Clock drivers D, C...Clock signals, L1 - L3 , L1a - L3a ...Wiring.
Claims (1)
上の段数のクロツクドライバと を備えたゲートアレー型の半導体集積回路におい
て、 前記クロツクドライバから各フリツプフロツプ
までの配線路の長さが等しくなるように、前記ク
ロツクドライバと各フリツプフロツプ間にツリー
状に配置された配線を備えた ことを特徴とする半導体集積回路。[Claims for Utility Model Registration] In a gate array type semiconductor integrated circuit comprising a plurality of flip-flops and one or more stages of clock drivers that supply clocks to each flip-flop, A semiconductor integrated circuit comprising wires arranged in a tree shape between the clock driver and each flip-flop so that the lengths of the wire paths are equal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4531890U JPH044432U (en) | 1990-04-27 | 1990-04-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4531890U JPH044432U (en) | 1990-04-27 | 1990-04-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH044432U true JPH044432U (en) | 1992-01-16 |
Family
ID=31559385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4531890U Pending JPH044432U (en) | 1990-04-27 | 1990-04-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH044432U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63229510A (en) * | 1987-03-18 | 1988-09-26 | Fujitsu Ltd | Clock skew calculating system |
-
1990
- 1990-04-27 JP JP4531890U patent/JPH044432U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63229510A (en) * | 1987-03-18 | 1988-09-26 | Fujitsu Ltd | Clock skew calculating system |
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