JPH0227749A - Forming method for integrated circuit pattern - Google Patents

Abstract

PURPOSE:To simplify a process and to shorten a turn-around-time by forming a pattern of a functional block unit on a chip by a mask slice type thereby to form a pattern of a LSI. CONSTITUTION:Patterns of first and second contact holes NA, NB are so regularly disposed together as to be contained in the gate region G and source, drain regions S/D of a transistor. A first wiring pattern is so disposed as to connect the patterns of the holes NA, NB in both the regions G and the regions S/D. A second wiring pattern is so disposed as to connect the patterns of the holes NA, NB. The second pattern is suitably altered on the basis of predetermined conditions for the formed stationary pattern to form an integrated circuit pattern. Thus, a turn-around-time is shortened.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a method for forming an integrated circuit pattern, particularly a technique for forming an LSI pattern by creating a pattern in units of functional blocks on a chip using a mask slicing method. The first process involves regularly arranging transistor patterns in cell units, and the first contact hole pattern, with the aim of simplifying the process, shortening turnaround time, and contributing to improved yields. and a second contact hole pattern are regularly arranged so as to be included in each of the gate region and source/drain region of the transistor, and the first wiring pattern is arranged in both the gate region and the source/drain region. a second step of arranging the patterns of the first and second contact holes to be connected;
and a third step of arranging a second wiring pattern so as to connect the second contact hole pattern, the fixed pattern formed in the first and second steps being set under predetermined conditions. Based on this, the second wiring pattern is appropriately changed to form an integrated circuit pattern.

[Industrial application field]

The present invention relates to a method for forming an integrated circuit pattern, and in particular,
Large-scale integrated circuits (L
The present invention relates to a technique for forming a pattern of SI).

[Prior art and problems to be solved by the invention]

The mask slicing method has become the mainstream method for developing integrated circuits (ASICs) for specific applications. Pattern until the end of the process (a certain number of transistors called basic cells)
In this method, only the fixed wiring pattern is changed depending on the product type, using a common wiring pattern (pattern). Specifically, as shown in FIG.
are arranged regularly, two-layer wiring of aluminum (AI) is arranged on the basic cells (not shown in FIG. 13), and connections between these cells are made on a fixed wiring area 3. This is done using two-layer wiring with the same <AI.

FIG. 14 shows a typical example of a transistor pattern. In the figure, ■Dlll represents a high potential power line pattern, VSS represents a low potential power line pattern, and (a) represents a transistor pattern corresponding to 1 basic cell (indicated by a dashed line 2). (b
), the hatched portion A indicates a region corresponding to the gate of the transistor. Also, in (c), hatched portions B and B14 indicate the P-type implantation region and N-type implantation region, respectively, for forming the source/drain (S/D) H region of the transistor. The hatched areas C6 and C0 represent P-channel transistors, and the hatched areas C□ and CHt represent N-channel transistors. In other words, four transistors form one basic cell. 2 are configured.

In this way, in the mask slicing method, a desired circuit is constructed by designing and creating various wiring patterns, but in that case, -II
A desired circuit is created using two types of AI wiring patterns and two types of contact hole (or via) patterns. Here, the first contact hole (hereinafter referred to as
] is the conductive region of the functional element (transistor) formed on the substrate and the first AI&! The second contact hole (hereinafter referred to as NB) is a hole for connecting the first A1 4sLA (hereinafter referred to as NB).
This is a hole for connecting the first AI wiring and the second AI wiring (hereinafter referred to as LB).

That is, in the conventional mask slicing method, when creating a wiring pattern after setting a fixed transistor pattern, there are two steps: creating the first AI wiring LA and creating the first contact hole NA. , second
A total of four steps are required: the step of creating the AI wiring LB and the step of creating the second contact ball NB, and each pattern is changed in each step according to the user's request or the product type. There was a need.

However, if a fixed pattern is set for some of these four steps, similar to the transistor pattern, and a desired circuit can be constructed by creating various patterns for the remaining steps, it is possible to The process is simplified by that amount, so turnaround time and
This is even more suitable from the viewpoint of shortening time and improving yield.

The present invention was created in view of the problems in the prior art, and provides a method for forming integrated circuit patterns that can simplify the process, shorten turn-around time, and contribute to improved yield. is intended to provide.

[Failure to solve the problem]

In order to solve the above-mentioned problems in the prior art, the method for forming an integrated circuit pattern of the present invention includes a first step of regularly arranging transistor patterns in cell units, a first step of arranging a first contact hole pattern, and a first step of regularly arranging transistor patterns in cell units. The second contact hole patterns are arranged regularly so as to be included in each of the gate region and the source/drain region of the transistor, and the first wiring pattern is arranged in the gate region of the transistor.
a second step of arranging the first and second contact hole patterns to be connected in both the 8i region and the source/drain region; and a third step of arranging the second wiring pattern, and the second wiring pattern is appropriately changed and integrated based on predetermined conditions with respect to the fixed pattern formed in the first and second steps. It is designed to form a circuit pattern.

[For production]

According to the above-described configuration, a desired LSI can be constructed by creating only the second wiring pattern in various ways. In other words, the three types of wiring patterns, the first contact hole, the first wiring, and the second contact hole, are fixed in the same way as the transistor pattern, so the overall process is better than the conventional one. is simplified. This contributes to shortening turn-around time and improving yield.

Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings.

〔Example〕

FIGS. 1(a) to 1(c) show the main steps of forming an LSI pattern as an embodiment of the present invention.

FIG. 1(a) shows the pattern up to the completion of the diffusion process, that is, the process of forming a transistor pattern.
2TR is a transistor pattern consisting of two P-channel transistors or N-channel transistors,
G is the gate fil region, S/D is the source/drain region,
P indicates a field area. In this embodiment, one cell is composed of two gate regions and two source/drain regions, that is, four transistors.

That is, in this step, the transistor patterns 2TR are regularly arranged in cell units.

FIG. 1(b) shows the first contact hole, that is, the NA
1 and 2, and the process of forming a pattern of a second contact hole, that is, a pattern of NB. In the diagram, small ○
The part indicated by is the pattern N of the first contact hole.
The portions indicated by A and large O represent the second contact hole pattern NB.

In this step, the first contact hole pattern NA
The second contact hole patterns NB and NA are both regularly arranged so as to be included in each of the gate region G and source/drain region S/D of the transistor.

Figure 1(c) is the first ^! This represents the process of forming wiring, that is, LA patterns. In the figure, the part indicated by a small O is the pattern NA of the first contact hole, and the part indicated by a large O
The part indicated by is the second contact hole pattern N
B. The part (+) shown by one thin solid line shows the LA pattern, especially the LA pattern shown by VDD is a high potential power supply line (voltage is 5V), and the part shown by Vss is the pattern of A. Low potential power line (voltage is OV)
represents.

In this step, the wiring pattern LA (excluding the power supply line) is arranged so that the first and second contact hole patterns NASNB are connected in both the gate high region G and source/drain region S/D of the transistor. be done. Also, the wiring pattern LA for the power supply line
is formed in one direction (in the illustrated example, vertically with respect to the plane of the paper) so as to pass over the second contact hole pattern NB arranged in the source/drain BM region S/D.

Therefore, by appropriately arranging the wiring pattern LB so as to connect the patterns NA and NB of the first and second contact holes, and appropriately changing the arrangement form based on predetermined conditions, a desired LSI can be constructed. can do.

Hereinafter, various patterns for each functional block created based on the process shown in FIG. 1 will be explained with reference to FIGS. 2 to 12.

'71742 Figures (a) to (C) show the configuration of an inverting circuit composed of one inverter. In the same figure (a), the part (1) indicated by the thick solid line - is the second A
It represents the pattern LB of the I wiring. That is, the wiring pattern LB connects the first and second contact hole patterns NA and NB. An equivalent representation of this circuit pattern is shown in (b), and a further representation of this circuit pattern as a gate representation is shown in (c). Corresponding parts in the figure are given the same reference numerals.

Similarly, FIGS. 3(a) to (c) show the configuration of an inverting circuit composed of two inverters, FIGS. 4(a) to (c) show the configuration of a two-man powered NAND gate, and FIGS. 5(a) to (c) is 3
The configuration of a human-powered NAND gate, Figures 6 (a) to (c) are the configurations of a 4-person powered NAND gate, and Figures 7 (a) to (c) are 3 composed of one two-person AND gate and one two-person Kaa gate. Configuration of human-powered gate circuit, Figure 8 (a)
) to (c) are one 3-man power and gate and one 2-man power
The configuration of a four-man powered gate circuit constructed by a human-powered gate, Figures 9(a) to (c) show the configuration of a four-man powered gate circuit constructed by two two-man powered AND gates and one two-man powered gate. Figures 10 (a) to (c) show the configuration of a 4-person gate circuit consisting of one 2-person AND gate and one 3-person CUT gate.
1(a) to (c) show the configuration of a four-man powered gate circuit consisting of one two-man powered OR gate, one two-man powered AND gate, and one two-man powered CUT gate, and FIGS. 12(a) to (c). c) shows the configuration of transfer gate TG.

In the embodiment described above, the wiring pattern of the LA is formed into the first and second contact hole patterns N in both the gate region and the source/drain region of the transistor.
Although the case where a desired circuit is constructed by appropriately arranging the LB wiring pattern after arranging A and NB to be connected has been described, as is clear from the gist of the present invention, the present invention is not limited thereto. 0 For example, after arranging the LB wiring pattern so that the first and second contact hole patterns NA and NB are connected in both the gate HI region and the source/drain region of the transistor, the second wiring pattern is placed. A desired circuit may be constructed by appropriately arranging them.

〔Effect of the invention〕

Conventionally, it was necessary to change each pattern in the four steps of NA, LA, NB, and LB according to the user's request or the product type, but according to the method for forming an integrated circuit pattern of the present invention, the LB ( A desired integrated circuit pattern can be formed simply by appropriately changing the pattern of (or LA).

In this way, the entire process is greatly simplified compared to the conventional method, which can greatly contribute to shortening turnaround time and, in turn, improving yield.

[Brief explanation of the drawing]

FIGS. 1(a) to (c) show an LS as an embodiment of the present invention.
A process diagram for explaining the method of forming the I pattern, FIGS. 2(a) to 2(c) are diagrams showing a first example of a pattern in functional block units created based on the process of FIG. 1,
(a) is a pattern diagram, (b) is an equivalent circuit diagram, (c) is a circuit diagram with gate representation, and Figures 3 (a) to (c) are functional block units created based on the process in Figure 1. In a diagram showing a second example of a pattern,
(a) is a pattern diagram, (b) is an equivalent circuit diagram, (c) is a circuit diagram with gate representation, and Figures 4 (a) to (c) are functional block units created based on the process in Figure 1. A diagram showing a third example of a pattern,
(a) is a pattern diagram, (b) is an equivalent circuit diagram, (c) is a circuit diagram with gate representation, and Figures 5 (a) to (c) are functional block units created based on the process in Figure 1. A diagram showing a fourth example of a pattern,
(a) is a pattern diagram, (b) is an equivalent circuit diagram, (c) is a circuit diagram with gate representation, and Figures 6 (a) to (c) are functional block units created based on the process shown in Figure 1. A diagram showing a fifth example of a pattern,
(a) is a pattern diagram, (b) is an equivalent circuit diagram, (c) is a circuit diagram with gate representation, and Figures 7 (a) to (c) are functional block units created based on the process in Figure 1. A diagram showing a sixth example of a pattern,
(a) is a pattern diagram, (b) is an equivalent circuit diagram, (c) is a circuit diagram with gate representation, and Figures 8 (a) to (c) are functional block units created based on the process in Figure 1. A diagram showing a seventh example of a pattern,
(a) is a pattern diagram, (b) is an equivalent circuit diagram, (c) is a circuit diagram with gate representation, and Figures 9 (a) to (c) are functional block units created based on the process in Figure 1. A diagram showing an eighth example of a pattern,
(a) is a pattern diagram, (b) is an equivalent circuit diagram, (c) is a circuit diagram with gate representation, and Figures 1O (a) to (c) are functional block units created based on the process in Figure 1. Diagram showing the ninth example of the pattern -
-(a) is a pattern diagram, (b) is an equivalent circuit diagram, (
c) is a circuit diagram in game display; FIGS. 11(a) to (c) are diagrams showing a tenth example of a pattern for each functional block created based on the process in FIG. 1; Pattern diagram, (b) equivalent circuit diagram, (c)
12(a) to 12(c) are diagrams showing an eleventh example of a pattern for each functional block created based on the process shown in FIG. 1; (a) is a pattern diagram; (b) is an equivalent circuit diagram, (c)
13A and 13B are diagrams for explaining the mask slicing method. FIG. 14 is a pattern diagram showing a typical example of a transistor cell. (Explanation of symbols) 2TR...Transistor pattern, NA, NB.
・Contact hole pattern, LA, LB...
Wiring pattern, G: gate 61 area of transistor, S/D: source/drain area of transistor.

Claims (1)

[Claims] A first step of regularly arranging transistor patterns (2TR) in cell units, a first contact hole pattern (NA, NB) and a second contact hole pattern (NB, NA) together with the gate region (G) and source region of the transistor.
A first wiring pattern (LA, LB) arranged regularly so as to be included in each of the drain regions (S/D), and
a second step of arranging the first and second contact hole patterns in both the gate region and the source/drain region so that they are connected; and connecting the first and second contact hole patterns. and a third step of arranging second wiring patterns (LB, LA) as shown in FIG. 1. A method for forming an integrated circuit pattern, characterized in that the integrated circuit pattern is formed by appropriately changing the pattern.