JPH0227785A - Integrated circuit element and its manufacture - Google Patents

Integrated circuit element and its manufacture

Info

Publication number
JPH0227785A
JPH0227785A JP63177821A JP17782188A JPH0227785A JP H0227785 A JPH0227785 A JP H0227785A JP 63177821 A JP63177821 A JP 63177821A JP 17782188 A JP17782188 A JP 17782188A JP H0227785 A JPH0227785 A JP H0227785A
Authority
JP
Japan
Prior art keywords
integrated circuit
manufacturing process
pads
circuit element
conductive wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63177821A
Other languages
Japanese (ja)
Inventor
Shinichiro Ishihara
伸一郎 石原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63177821A priority Critical patent/JPH0227785A/en
Publication of JPH0227785A publication Critical patent/JPH0227785A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps

Landscapes

  • Structure Of Printed Boards (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、液晶表示装置等二次元的な駆動を必要とする
表示素子もしくは受光素子を動作させる集積回路素子お
よびこの集積回路素子を製造する方法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an integrated circuit element for operating a display element or a light receiving element that requires two-dimensional driving, such as a liquid crystal display device, and a method for manufacturing this integrated circuit element. It is something.

従来の技術 従来の集積回路素子の実装方法について図面を用いて説
明する。第7図はスイッチング素子アレー基板上に集積
回路素子を実装した従来例を示すものである。
2. Description of the Related Art A conventional method for mounting an integrated circuit device will be described with reference to the drawings. FIG. 7 shows a conventional example in which integrated circuit elements are mounted on a switching element array substrate.

ガラス基板1上にスイッチング素子アレー2があり、こ
の周囲にY軸駆動用の集積回路素子3とX軸駆動用の集
積回路素子4が実装されている。
A switching element array 2 is provided on a glass substrate 1, and an integrated circuit element 3 for driving the Y-axis and an integrated circuit element 4 for driving the X-axis are mounted around this.

集積回路素子3はスイッチング素子アレー2の上下二方
向から信号を供給される様に配置されている。集積回路
素子3および集積回路素子4のパスライン5.6はガラ
ス基板1の周囲に配置され、外部取り出し端子7に続い
ている。
The integrated circuit element 3 is arranged so as to be supplied with signals from both the upper and lower directions of the switching element array 2. The pass lines 5 , 6 of the integrated circuit elements 3 and 4 are arranged around the glass substrate 1 and continue to the external lead terminals 7 .

発明が解決しようとする課題 しかし、第7図に示したとおり従来の構成では、パスラ
イン5.6には、立体交差する領域8が存在するため信
号の絶縁の点で問題があり、また、パスライン5.6は
必然的に基板1の周辺に配置されるため、層間絶縁膜(
図示せず)の信頼性の低下、ピンホール等の欠陥の発生
と言う問題もあった。
Problems to be Solved by the Invention However, as shown in FIG. 7, in the conventional configuration, the path lines 5 and 6 have a three-dimensionally intersecting region 8, which poses a problem in terms of signal insulation. Since the pass line 5.6 is necessarily arranged around the substrate 1, the interlayer insulating film (
There were also problems such as decreased reliability (not shown) and occurrence of defects such as pinholes.

課届を解決するための手段 本発明は、上述の問題点を解決するために、四辺形の一
辺に平行に配置された信号出力用パッド、上記の辺に対
向する一辺に平行に配置された集積回路駆動用パッドお
よび集積回路用パターンが存在しない領域に複数のパッ
ドを具備しかつ四辺形の上記二辺に直交する他の二辺に
平行に配置された導電配線を備えたことを特徴とする集
積回路素子を絶縁基板」二に実装するというものである
Means for Solving the Problems The present invention solves the above-mentioned problems by providing a signal output pad arranged parallel to one side of a quadrilateral, and a signal output pad arranged parallel to one side opposite to the above-mentioned side. It is characterized by comprising a plurality of pads in areas where there are no integrated circuit driving pads and integrated circuit patterns, and conductive wiring arranged parallel to the other two sides orthogonal to the above two sides of the quadrilateral. The integrated circuit elements are mounted on an insulating substrate.

作用 本発明は、上述の構成により、絶縁基板上でのパスライ
ン同士の立体交差がなく、集積回路素子を実装するだけ
で自動的に信頼性の高い立体配線を完了する。また、従
来に比べ、パスラインを絶縁基板のより内側に配置する
ことが可能なため、配線の信頼性を向上させることがで
きる。
According to the present invention, with the above-described configuration, there is no three-dimensional intersection between path lines on an insulating substrate, and highly reliable three-dimensional wiring is automatically completed simply by mounting an integrated circuit element. Furthermore, since the pass line can be placed further inside the insulating substrate than in the past, the reliability of the wiring can be improved.

また、集積回路用パターンの製造工程と、集積回路用パ
ターンが存在しない領域に配置された導電配線の製造工
程とを分離することにより、製造工程が簡易化する。す
なわち、絶縁基板上実装用集積回路素子は集積回路用パ
ターンが同一であるものが多い。そこで集積回路用パタ
ーンが存在する領域と、集積回路用パターンが存在しな
い領域に配置された導電配線とを同時に製造した場合に
比べて、本発明による製造方法によれば集積回路用パタ
ーンが同一で導電配線のみ異なる集積回路素子をより簡
単に製造することができる。すなわち、集積回路用パタ
ーンの製造工程を全(変えることなしに、集積回路素子
端の導電配線のみを実装用絶縁基板上の配線の都合に合
わせて製造することができ、同時に製造した場合に比べ
て、製造工程が簡易化する。
Further, the manufacturing process is simplified by separating the manufacturing process of the integrated circuit pattern from the manufacturing process of the conductive wiring arranged in the area where the integrated circuit pattern does not exist. That is, many integrated circuit elements for mounting on an insulating substrate have the same integrated circuit pattern. Therefore, compared to the case where the area where the integrated circuit pattern exists and the conductive wiring placed in the area where the integrated circuit pattern does not exist are manufactured at the same time, according to the manufacturing method of the present invention, the integrated circuit pattern is the same. Integrated circuit elements that differ only in conductive wiring can be manufactured more easily. In other words, without changing the entire integrated circuit pattern manufacturing process, only the conductive wiring at the end of the integrated circuit element can be manufactured to match the wiring on the insulating board for mounting, which is faster than when manufacturing at the same time. This simplifies the manufacturing process.

実施例 以下、本発明の一実施例における集積回路素子について
図面を用いて詳しく説明する。
Embodiment Hereinafter, an integrated circuit element according to an embodiment of the present invention will be explained in detail with reference to the drawings.

第1図は絶縁基板上実装用集積回路素子11の平面図で
ある。以下の説明がわかりやすいように集積回路素子の
2つの主面のうちパッドが存在する側の主面をその反対
側の主面から透過して見たものである。すなわち、パッ
ドが存在する側の集積回路素子の主面をそのまま見た像
の反転対称図となっている。12で示した領域は集積回
路用のパターンが存在する領域である。また四辺形より
なる集積回路素子の一辺に平行に信号出力用パッド13
が、上記の辺に対向する一辺に平行に集積回路駆動用パ
ッドおよびダミーヘッド14が配置されている。信号出
力用パッド13は、パッドのほぼ全数が出力用として使
用されるが、集積回路駆動用パッド14は、このなかの
いくつかしか実際には使用されず、のこりは主として絶
縁基板上実装の接着強度及び信頼性を保つために使用さ
れる。ここでは、このパッドをダミーパッドと呼ぶ。
FIG. 1 is a plan view of an integrated circuit element 11 for mounting on an insulating substrate. In order to make the following explanation easier to understand, the figure shows the main surface on the side where the pad is present among the two main surfaces of the integrated circuit element as seen through the main surface on the opposite side. In other words, it is an inverted symmetrical view of the main surface of the integrated circuit element on the side where the pad is present. The area indicated by 12 is an area where a pattern for an integrated circuit exists. In addition, a signal output pad 13 is parallel to one side of the quadrilateral integrated circuit element.
However, an integrated circuit driving pad and a dummy head 14 are arranged parallel to one side opposite to the above-mentioned side. Almost all of the signal output pads 13 are used for output, but only some of the integrated circuit drive pads 14 are actually used, and the rest are mainly used for adhesive mounting on an insulating substrate. Used to maintain strength and reliability. Here, this pad is called a dummy pad.

15.16は、パッド類に合わせてパスラインの順番を
変更するためのパッドであり、集積回路用パターンの片
側だけでなく、両側に形成しても良い。また、19.2
0は、パスライン順変更用パッド15.16を接続する
導電配線である。パスライン順変更用パッド17.1g
も同様に導電配線21122で接続する。
Pads 15 and 16 are used to change the order of pass lines according to the pads, and may be formed not only on one side of the integrated circuit pattern but also on both sides. Also, 19.2
0 is a conductive wiring connecting the pass line order change pads 15 and 16. Pass line order change pad 17.1g
are similarly connected by conductive wiring 21122.

第2図は、絶縁基板上のパスラインのパターンを示した
ものである。すなわち、23.24.25は集積回路素
子11駆動用のパスラインであり、それぞれ集積回路駆
動用パッド26.27.28に接続されるべきものであ
る。
FIG. 2 shows a pattern of pass lines on an insulating substrate. That is, 23, 24, and 25 are pass lines for driving the integrated circuit element 11, and are to be connected to integrated circuit driving pads 26, 27, and 28, respectively.

第3図は、第1図の集積回路素子11を、第2図の絶縁
基板上に実装した様子を示すものである。
FIG. 3 shows how the integrated circuit element 11 of FIG. 1 is mounted on the insulating substrate of FIG. 2.

第7図に示したように集積回路素子をほぼ直線上に複数
個並べて実装する場合において、第3図に示したように
パスライン23.24.25は、絶縁基板上での立体交
差がなく、集積回路素子11を実装するだけで、導電配
線19.20により自動的に信頼性の高い立体配線を完
了する。
When a plurality of integrated circuit elements are mounted in a substantially straight line as shown in FIG. , just by mounting the integrated circuit element 11, highly reliable three-dimensional wiring is automatically completed using the conductive wirings 19 and 20.

第4図は、集積回路素子駆動用のパスライン3Oが第2
図に示したものよりも多い場合を示したものである。本
実施例の集積回路素子11を使用した場合、絶縁基板上
のパターンを変更するだけで、最大4本のパスライン順
を変更することができた。
In FIG. 4, the pass line 3O for driving the integrated circuit element is connected to the second
This figure shows a case in which there are more cases than those shown in the figure. When the integrated circuit element 11 of this example was used, the order of up to four pass lines could be changed by simply changing the pattern on the insulating substrate.

第5図は、導電配線19.20.21.22に、パスラ
イン変更用パッド40を3点以上配置した様子を示した
ものである。この配置方法によれば、絶縁基板上の配線
パターンにより柔軟性を持たせることができ、さらに複
数のパッドで同一バスラインに接続することにより、パ
ッドとパスラインとの接触抵抗を下げることができる。
FIG. 5 shows how three or more pass line changing pads 40 are arranged on the conductive wiring 19, 20, 21, 22. According to this arrangement method, the wiring pattern on the insulating substrate can be made more flexible, and by connecting multiple pads to the same bus line, the contact resistance between the pads and the pass line can be lowered. .

  第6図は、第1図の集積回路素子を用いたスイッチ
ング素子アレーを示したものである。従来に比ベバスラ
イン5.6はガラス基板1のより内側に配置されるため
、パスライン5.6の配線の信頼性を向上させることが
できる。なお、本実施例では集積回路素子の製造方法に
ついては特に規定を設けなかったが、以下に述べる方法
で製造することにより製造工程を簡易化する事ができる
。まず、集積回路用パターン領域を従来の集積回路製造
プロセスを用いて作成する。ただし、集積回路用パター
ン領域12の両端に、導電配線配置領域101.102
を残しておく。最終配線パターンまたは低抵抗の配線を
形成する工程において導電配線19.20.21.22
を形成し、保護膜(図示せず)を通常の集積回路製造プ
ロセスを用いて形成し、さらに通常プロセスにおいて、
パッドを形成した。
FIG. 6 shows a switching element array using the integrated circuit elements of FIG. 1. Compared to the conventional case, the pass line 5.6 is arranged more inside the glass substrate 1, so that the reliability of the wiring of the pass line 5.6 can be improved. In this embodiment, no particular regulations were set regarding the method of manufacturing the integrated circuit element, but the manufacturing process can be simplified by manufacturing using the method described below. First, an integrated circuit pattern area is created using a conventional integrated circuit manufacturing process. However, conductive wiring placement areas 101 and 102 are provided at both ends of the integrated circuit pattern area 12.
Leave it. Conductive wiring in the process of forming the final wiring pattern or low resistance wiring 19.20.21.22
A protective film (not shown) is formed using a normal integrated circuit manufacturing process, and further, in the normal process,
A pad was formed.

このように、集積回路パターン領域12の製造工程と、
導電配線配置領域101.102の製造工程とを分離し
た。なお、この場合、導電配線配置領域を、集積回路用
パターンの両側に形成したが、片側のみに形成してもよ
い。
In this way, the manufacturing process of the integrated circuit pattern area 12,
The manufacturing process for the conductive wiring arrangement regions 101 and 102 is separated. In this case, the conductive wiring arrangement regions are formed on both sides of the integrated circuit pattern, but they may be formed only on one side.

この導電配線配置領域101.102を両方合わせても
、集積回路素子の幅の増加は0. 5mm程度にしかな
らず、集積回路素子を大きくすることもなく立体交差用
の配線を実現することができる。また集積回路用パター
ン領域12の製造工程と、導電配線配置領域101.1
02の製造工程とを分離することにより、集積回路用パ
ターン領域12が同一で、かつ導電配線配置領域101
.102のみが異なる集積回路素子をより簡易に製造す
ることができる。
Even if both conductive wiring placement areas 101 and 102 are combined, the width of the integrated circuit element increases by 0. It is only about 5 mm, and wiring for grade crossings can be realized without increasing the size of the integrated circuit element. Also, the manufacturing process of the integrated circuit pattern area 12 and the conductive wiring arrangement area 101.1.
By separating the manufacturing process of 02, the integrated circuit pattern area 12 is the same, and the conductive wiring placement area 101 is the same.
.. Integrated circuit elements that differ only in 102 can be manufactured more easily.

発明の効果 以上の説明から明らかなように、本発明の集積回路素子
は、四辺形の一辺に平行に配置された信号出力用パッド
、上記の辺に対向する一辺に平行に配置された集積回路
駆動用パッドおよび集積回路用パターンが存在しない領
域に複数のパッドを具備しかつ四辺形の上記二辺に直交
する他の二辺に平行に配置された導電配線を備えるとい
う構成により、従来存在した絶縁基板上でのパスライン
の立体交差をなくシ、配線の信頼性をあげることができ
るという効果を有する。
Effects of the Invention As is clear from the above description, the integrated circuit element of the present invention includes a signal output pad arranged parallel to one side of a quadrilateral, and an integrated circuit arranged parallel to one side opposite to the above-mentioned side. It has a structure in which a plurality of pads are provided in areas where there are no driving pads and integrated circuit patterns, and conductive wiring is arranged parallel to the other two sides of the quadrilateral that are orthogonal to the above two sides. This has the effect of eliminating three-dimensional intersections of pass lines on the insulating substrate and improving the reliability of wiring.

また、集積回路用パターンの製造工程と集積回路用パタ
ーンが存在しない領域に配置された導体配線の製造工程
とを分離することにより、集積回路用パターンの製造工
程を全く変えることなしに、集積回路用パターンが存在
しない領域に配置された導電配線のみを実装用絶縁基板
上の配線の都合に合わせて製造することができ、同時に
製造した場合に比べて、製造方法が簡易になるという効
果も有する。
In addition, by separating the manufacturing process for integrated circuit patterns and the manufacturing process for conductor wiring placed in areas where integrated circuit patterns do not exist, integrated circuit patterns can be manufactured without changing the manufacturing process for integrated circuit patterns at all. It is possible to manufacture only the conductive wiring placed in the area where there is no pattern for mounting according to the wiring on the insulating board for mounting, and it also has the effect that the manufacturing method is simpler than when manufacturing at the same time. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例における集積回路素子の平面
図、第2図は本発明による集積回路素子を実装される側
の絶縁基板上のパスラインパターンを示す平面図、第3
図は第1図の集積回路素子を第2図の絶縁基板上に実装
した様子を示した平面図、第4図は第2図とは別のパス
ラインパターンを具備する絶縁基板上に第1図の集積回
路素子を実装した様子を示した平面図、第5図は導線配
線上にパスライン変更用パッドを3点以上配置させた集
積回路素子を示した平面図、第6図は本発明における集
積回路素子を用いたスイッチング素子アレーを示した平
面図、第7図は従来からの集積回路素子を用いたスイッ
チング素子アレーを示した平面図である。 11・・・集積回路素子、  12 @・・集積回路用
パターン領域、   13・・・信号出力用パッド、 
 14・・・集積回路駆動用/XI ’yドおよびダミ
ーパッド、   15、16、17、18.40・・・
パスライン順変更パッド、19.20.21.22・Φ
・導電配線、   101.102・番拳導電配線配置
領域。 代理人の氏名 弁理士 栗野重孝 はか1名第 図 8、べ゛ズライン遼−覧イ貰カへ
FIG. 1 is a plan view of an integrated circuit device according to an embodiment of the present invention, FIG. 2 is a plan view showing a pass line pattern on an insulating substrate on which the integrated circuit device according to the present invention is mounted, and FIG.
The figure is a plan view showing how the integrated circuit device of FIG. 1 is mounted on the insulating substrate of FIG. 2, and FIG. FIG. 5 is a plan view showing an integrated circuit device in which the integrated circuit device shown in FIG. FIG. 7 is a plan view showing a switching element array using integrated circuit elements, and FIG. 7 is a plan view showing a switching element array using conventional integrated circuit elements. 11... Integrated circuit element, 12 @... Integrated circuit pattern area, 13... Signal output pad,
14... Integrated circuit driving/XI 'y pad and dummy pad, 15, 16, 17, 18.40...
Pass line order change pad, 19.20.21.22・Φ
・Conductive wiring, 101.102・Banken conductive wiring placement area. Name of agent: Patent attorney Shigetaka Kurino Please see Figure 8, Base Line - Click here to receive a copy.

Claims (2)

【特許請求の範囲】[Claims] (1)四辺形の一辺に平行に配置された信号出力用パッ
ド、上記の辺に対向する一辺に平行に配置された集積回
路駆動用パッドおよび集積回路用パターンが存在しない
領域に複数のパッドを具備し、かつ四辺形の上記二辺に
直交する他の二辺に平行に配置された導電配線を備えた
ことを特徴とする集積回路素子。
(1) A signal output pad placed parallel to one side of the quadrilateral, an integrated circuit driving pad placed parallel to one side opposite the above side, and multiple pads placed in an area where there is no integrated circuit pattern. 1. An integrated circuit element comprising: conductive wiring arranged parallel to two other sides perpendicular to the two sides of the quadrilateral.
(2)四辺形の一辺に平行に配置された信号出力用パッ
ド、上記の辺に対向する一辺に平行に配置された集積回
路駆動用パッドおよび集積回路用パターンが配置された
領域の製造工程と、集積回路用パターンが存在しない領
域に複数のパッドを具備し、かつ四辺形の上記二辺に直
交する他の二辺に平行に配置された導電配線の製造工程
とを分離することを特徴とする集積回路素子の製造方法
(2) Manufacturing process for signal output pads arranged parallel to one side of the quadrilateral, integrated circuit drive pads arranged parallel to one side opposite the above-mentioned side, and the area where the integrated circuit pattern is arranged. , a plurality of pads are provided in an area where an integrated circuit pattern does not exist, and the manufacturing process is separated from the manufacturing process of conductive wiring arranged parallel to the other two sides orthogonal to the above two sides of the quadrilateral. A method for manufacturing an integrated circuit device.
JP63177821A 1988-07-15 1988-07-15 Integrated circuit element and its manufacture Pending JPH0227785A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63177821A JPH0227785A (en) 1988-07-15 1988-07-15 Integrated circuit element and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63177821A JPH0227785A (en) 1988-07-15 1988-07-15 Integrated circuit element and its manufacture

Publications (1)

Publication Number Publication Date
JPH0227785A true JPH0227785A (en) 1990-01-30

Family

ID=16037690

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63177821A Pending JPH0227785A (en) 1988-07-15 1988-07-15 Integrated circuit element and its manufacture

Country Status (1)

Country Link
JP (1) JPH0227785A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5432488A (en) * 1992-12-29 1995-07-11 Mitsumi Electric Co., Ltd. Electrical signal filter
US5592199A (en) * 1993-01-27 1997-01-07 Sharp Kabushiki Kaisha Assembly structure of a flat type device including a panel having electrode terminals disposed on a peripheral portion thereof and method for assembling the same
JP2004004738A (en) * 2002-04-30 2004-01-08 Samsung Electronics Co Ltd Drive integrated circuit package and chip-on-glass liquid crystal display device using the same
US8031150B2 (en) 1999-04-16 2011-10-04 Samsung Electronics Co., Ltd. Liquid crystal display panel with signal transmission patterns

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5432488A (en) * 1992-12-29 1995-07-11 Mitsumi Electric Co., Ltd. Electrical signal filter
US5592199A (en) * 1993-01-27 1997-01-07 Sharp Kabushiki Kaisha Assembly structure of a flat type device including a panel having electrode terminals disposed on a peripheral portion thereof and method for assembling the same
US5670994A (en) * 1993-01-27 1997-09-23 Sharp Kabushiki Kaisha Assembly structure of a flat type device including a panel having electrode terminals disposed on a peripheral portion
US8031150B2 (en) 1999-04-16 2011-10-04 Samsung Electronics Co., Ltd. Liquid crystal display panel with signal transmission patterns
JP2004004738A (en) * 2002-04-30 2004-01-08 Samsung Electronics Co Ltd Drive integrated circuit package and chip-on-glass liquid crystal display device using the same

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