JPH022778A - Method for interfacing with cpu - Google Patents

Abstract

PURPOSE:To surely perform readout and write by initializing the internal address of a control circuit by outputting a control signal before and after the readout/write operation of information by a CPU, respectively, and outputting the normal/defective state of the readout/write on an information line synchronizing with the control signal by the control circuit. CONSTITUTION:At the time of performing the write, the CPU initializes the internal address of the control circuit 2 by setting a signal line 3 at low output 12, and outputting a negative pulse 13 to a signal line 4. and inputs the information 15 in unit of byte sequentially to a signal line 6 synchronizing with the negative pulse on a signal line 5. When the information 15 shows D7='1', the CPU waits the write. By the output of the last pulse 18, it is set as D7='1' synchronizing with the negative pulse on the signal line 4. When the signal D7 is set at '1', the regulated number (n) information 15 are written in order, and when it is D7='0', an operation is repeated from the negative pulse 13. By employing such constitution, the position of the information can be shown clearly, and no address line is required. Also, it is possible to surely perform the readout/write repeatedly by confirming the incompletion of the read/write. At the time of performing the readout from the control circuit 2, the readout/write can be surely performed almost similarly by setting a signal line 19 at high output 19.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a CPU interface method.

(Prior art) Figure 4 shows C in a conventional CPU interface method.
It is a block circuit diagram showing the connection between the PU and the control circuit,
FIG. 5 is a timing chart of each part of FIG. 4. C
The control circuit 32 that controls communication between the PtJ 31 and the outside includes 0 address lines (A to A) 33, a data read timing signal line 34, and 8 data lines (D,
~D, ) 35. The control circuit 32 is composed of a ROM, is connected to multiple transmission lines, and controls communication with the outside. In the CPU interface method in the conventional communication system, the CPU 31 outputs an address signal indicating the data position, that is, the address, to the address line 33 to the control circuit 32, and also outputs a data read timing signal to the data read timing signal line 34. Outputs a certain negative clock pulse. The control circuit 32 synchronizes with this negative clock pulse by using the data line 35 to
The address signal shown in FIG. 5(a) is output to. C
PU 1 receives this address signal output to data line 35 and processes it internally. Such an operation is performed for each data and is repeated a prescribed number of times, that is, 2'1 times.

(Problem to be solved by the invention) However, in the conventional CPU interface method,
If the negative clock pulse shown in FIG. 5(b) is canceled due to the influence of noise and is not input to the control circuit 32, the control circuit 32 does not output data to the data line 35, so the CPUI becomes unstable. There is a problem that data is taken in and erroneous processing is performed therein, and there is also a problem that the number of address lines 33 increases as the number of data increases.

The present invention has been made in view of the above circumstances, and is based on the CP
It is an object of the present invention to provide a CPU interface method that can reliably read or write data without increasing the number of tangents to U.

(Means for Solving the Problems) In order to achieve the above object, according to the present invention, one or more bytes of data are transferred in byte units between a CPU and a control circuit that controls communication with the outside. In the CPU interface method of reading data from the control circuit to the CPU and writing data from the CPU to the control circuit, the CPU outputs control signals to the control circuit before and after reading/writing data, respectively. initialize the position of the data to be output to the data line,
A CPU interface method is provided in which the control circuit outputs a signal indicating the quality of the read/write result and a signal indicating the presence or absence of a data read request onto the data line in synchronization with the control signal.

(Function) The CPU outputs a control signal to the control circuit before and after a data read/write operation to initialize the internal address of the control circuit, and the control circuit performs read/write operations on the data line in synchronization with this control signal. Outputs pass/fail status.

(Example) Hereinafter, an example of the present invention will be described in detail based on the accompanying drawings.

FIG. 1 is a block circuit diagram showing the connection between the CPUI and the control circuit 2 for explaining the CPU interface method of the present invention, and FIG. 2 is a timing chart of each part when writing from the CPUI to the control circuit 2. , FIG. 3 is a timing chart of each part during reading from the control circuit 2 to the CPUI. The CPUI and control circuit 2 are read/
Write signal (R/W) line 3, control signal (SRC, 5)
tatusRead C1ear) line 4, read/write clock signal (RWP, Read Wri
te Pulse) line 5, and data line (D, ~D,
)6.

First, when writing data from the CPU 1 to the control circuit 2, cput sets the read/write signal line 3 to the "low" output 12 in FIG. 2(a). After that, the CPUI outputs the negative pulse 13 shown in FIG. 2(b) to the control signal line 4,
The position of the data area to be written in the control circuit 2, that is, the internal address, is initialized so that the data output from the CPUI to the data line 6 in byte units can be written in order from the first data #1. Furthermore, the CPUI is negative pulse 1
For example, the data 15 outputted from the control circuit 2 to the data line 6 in synchronization with D? - If it is rOJ, write quasi-WO
K and D? If =rlJ, then write preparation is NG, input data 15, output negative pulse to read/write clock signal line 5 for the specified number of bytes 0 times when D7 - "0", and read/write clock signal line 5
Data is transferred to data line 6 in synchronization with the negative pulse of Figure 2 (
Data #1, data #2, etc. are output in order as shown in d). The control circuit 2 inputs the data output to the data line 6 in synchronization with the negative pulse of the read/write clock signal 5. Data is written in the data area of the control circuit 2 in order from data #1 to data #n. Data 15 is D? -rlJ, the CPUI waits for writing.

When the last n-th pulse 18 in FIG. 2(C) is output from the CPU to the read/write clock signal line 5, the pulse is output from the control circuit 2 to the data line 6 in synchronization with the negative pulse of the control signal line 4. Is the output data D? = ' I J
Set it so that After outputting the negative pulse 18 shown in FIG. 2(b), the CPU connects the control signal line 4 again to the control signal line 4 shown in FIG. 2(b).
2 (d), which is output from the control circuit 2 to the data line 6 in synchronization with this negative pulse 16.
), if the signal 17 indicating the quality of writing is ='l', the prescribed number n of data has been written in good order. When the signal 17 is Dq='0'', the same procedure is repeated again from the output of the negative pulse 13 in FIG. 2(b).

On the other hand, when the CPUI reads data from the control circuit 2, the CPUI connects the read/3 write signal line 3 as shown in FIG.
a) "High J output 19. After that, the CPU 1 outputs the negative pulse 20 shown in FIG. 3(b) to the control signal line 4,
The internal address of the data read from the control circuit 2 is initialized so that the data output from the control circuit 2 to the data line 6 can be written in order from the first data #1. Furthermore, C
The PU1 receives the data 22 outputted from the control circuit 2 to the data line 6 in synchronization with the negative pulse 20 in FIG.
If D6 = 'l', the data read request is '
If "No", manually input data 22 and get Db = ' 0
”, a negative pulse is output to the read/write clock signal line 5 for a specified number of bytes, that is, n times, and the control circuit 2 outputs data to the data line 6 in synchronization with the negative pulse of the read/write clock signal line 5. Data #1, data #2, etc. are output in order. The CPUI inputs the data output to the data line 6 in synchronization with the negative pulse of the read/write clock signal line 5. Data is CP
Loaded into the UI in an orderly manner. Data #l is D6='
At lJ, the CPUI waits for reading.

CPLI 1 to read/write clock signal line 5
When the last n-th negative pulse 25 in FIG. 3(C) is output, the data output from the control circuit 2 to the data line 6 in synchronization with the negative pulse of the control signal line 4 is D6=rlJ. Set it so that 33rd (c) negative pulse 25
After the output of , the CPU returns the control signal line 4 to the
) outputs a negative pulse 23. If the data read request signal 24 outputted from the control circuit 2 to the data line 6 in synchronization with this negative pulse 23 is D6='lJ, the specified number of data has been read out in good order. If the read request signal 24 is Db="0", the third
The same procedure is repeated starting from negative pulse 20 in Figure (b).

(Effects of the Invention) As explained above, according to the present invention, data of one byte or more is transmitted between the CPU and the control circuit that controls communication with the outside via the data line from the control circuit. In the CPU interface method of reading data to the CPU and writing data from the CPU to the control circuit, the CPU outputs a control signal to the control circuit before and after reading/writing data, and connects the data line to the control circuit. The position of the data to be output is initialized, and the control circuit outputs a signal indicating the quality of the read/write result and a signal indicating the presence or absence of a data read request on the data line in synchronization with the control signal. , when reading/writing, the data order, that is, the address, is always initialized, so if you read/write data in the correct order, the location of the data will be clear.
As a result, address lines are no longer required, so the number of connection points can be reduced, the number of CPU ports and the number of control circuit terminals can be saved, and since it is possible to confirm whether a read/write is completed or not, it is possible to confirm whether the read/write is completed or not. By performing rereading/rewriting, it is possible to obtain the effect that reading/writing can be performed reliably.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing the connection between the CPUI and the control circuit 2 to explain the CPU interface method of the present invention, and FIG. Timing chart, Figure 3 is the 1st
A timing chart of each part when reading data from the control circuit 2 to the CPU shown in the figure, FIG. 4 is a block circuit diagram showing the connection between the CPU and the control circuit in the conventional CPU interface method, and FIG. It is a timing chart of each part of a figure. 1.31...cpu, 2.32...control circuit, 3.
...Read/write signal line, 4...Control signal line,
5... Read/write clock signal line, 6, 35
...Data line, 33...Address line, 34...Data read timing signal line.

Claims (1)

[Claims] Between a control circuit that controls communication between the CPU and the outside, data of one or more bytes is read from the control circuit to the CPU via a data line in byte units, and the data is read out from the control circuit to the CPU via a data line.
In the CPU interface method for writing data from U to the control circuit, the CPU outputs a control signal to the control circuit before and after reading/writing data to determine the position of the data to be input/output to the data line. A method for interfacing a CPU, characterized in that the control circuit outputs a signal indicating the quality of the read/write result and a signal indicating the presence or absence of a data read request on the data line in synchronization with the control signal. .