JPH0227813B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a bipolar transistor with excellent high frequency characteristics suitable for integrated circuits.

In recent years, in order to realize bipolar transistors with excellent high frequency characteristics and integrated circuits using the transistors, it has become common practice to form the emitter region of an NPN transistor into a mesa structure. FIG. 1 shows the structure of this type of transistor and its simple manufacturing method.

In the process diagram of FIG. 1, first, in step a, a P-type base region 2 and a shallow trench doped with arsenic are formed on the surface of an N-type silicon substrate 1, which will serve as a collector region.
The N ⁺ layer 3 is formed by diffusion in an oxygen atmosphere. Above N ⁺
After etching and removing the silicon oxide film on the N ⁺ layer 3 that remains after the diffusion treatment for forming the layer 3, a silicon oxide film 4 is deposited on the entire surface using a CVD method or the like on the collector region 1 and the base region 2. Then, a silicon nitride film 5 and a polycrystalline silicon film 6 are deposited. Then, a predetermined photoresist pattern 7 is provided on the outermost portion.

In step b, the polycrystalline silicon film 6 is etched using the positive photoresist pattern 7, such as OFPR-800 (trade name), formed on the surface of the polycrystalline silicon film 6 by a conventional method as a mask, and then, After removing the photoresist pattern 7, using the polycrystalline silicon film 6a of the same shape as a mask, the silicon nitride film 5 immediately below is etched with hot phosphoric acid to form a silicon nitride film 5a of the same shape.

In step c, the N ⁺ layer 3 is etched using the silicon nitride film 5a as a mask to form an N ⁺ type emitter region 3a. During this etching process, the polycrystalline silicon film 6a above the mask is also etched away.

In step d, the exposed surfaces of the P type base region 2 and the N ⁺ type emitter region 3a are selectively oxidized in an oxidizing atmosphere at a temperature of about 900° C. to form a silicon oxide film 4a on the surface.

In the conventional method shown ^{in FIG .} The etching rate of this layer 3 is significantly higher than that of silicon. Therefore, when etching the N ⁺ layer 3 to form the N-type emitter region 3a, etching with a hydrofluoric acid solution results in a large amount of undercut with respect to the silicon nitride film 5a, which is a mask, and the emitter region 3a is etched. The control and reproducibility of the pattern size and shape of 3 is poor, and in the manufacturing process described above, it is difficult to determine the end point of etching of the N ⁺ layer 3. There was a problem of large variations in characteristics.

An object of the present invention is to provide a bipolar transistor manufacturing method that solves the above problems.

In the present invention, a silicon nitride film formed directly or through an oxide film on the surface of a semiconductor substrate is selectively etched into an annular shape to separate it into an inner island-like part and an outer part, and then the silicon nitride film is separated into an inner island-like part and an outer part. A step of forming a predetermined region by implanting impurity ions that give a conductivity type opposite to that of the substrate into the semiconductor substrate under the selective etching using as a mask, and a silicon nitride film remaining in the inner island-like portion. Alternatively, a step of removing the silicon nitride film and the silicon oxide film immediately below it to expose the semiconductor substrate surface, forming an epitaxial layer of the same conductivity type on the exposed semiconductor substrate portion, and then removing the same epitaxial layer. This method of manufacturing a semiconductor device includes a step of converting a lower portion or a top portion of the semiconductor substrate into a layer of an opposite conductivity type.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be explained in detail by way of examples and with reference to the drawings.

In FIG. 2, a to f illustrate a method of manufacturing a bipolar integrated circuit, which is an embodiment of the present invention.

In step a, the N-type silicon substrate 10, which will become the collector region of the NPN transistor, is thermally oxidized in an oxidizing atmosphere to form a silicon oxide film 11a with a thickness of 300 nm.
After growing the silicon oxide film 11a to a thickness of about 500 Å, a silicon nitride film 12 is deposited to a thickness of about 6000 to 8000 Å on the silicon oxide film 11a by plasma deposition, and then a positive photoresist such as OFPR-800 (trade name) is deposited. Using the film pattern as a mask, the silicon nitride film 12 is selectively removed in an annular manner by plasma dry etching to form an island portion 12a.

In step b, the silicon nitride films 12, 12a
Using this as a mask, boron ions are implanted using the ion implantation method at an implantation energy of 60 KeV and a dose of approximately 1×10 ¹⁵ cm ^-2 to form a P ⁺ layer 13 that will become a P-type base contact region (P-type graft base region). Then, after annealing in a nitrogen atmosphere at a temperature of about 850 to 900°C, it is oxidized for about 100 minutes in an oxidizing atmosphere at a temperature of about 900 to 950°C. As a result, oxidation progresses in the region of the P ⁺ layer 13 as it diffuses, and a silicon oxide film 11b with a thickness of about 3000 to 4000 Å is formed, and at the same time, a portion of the silicon nitride films 12 and 12a also has a thickness of about 200 to 300 Å. An oxidized silicon oxide film 11c is formed, and the difference in thickness between the silicon nitride films 12 and 12a and the thick silicon oxide film 11b on the P ⁺ layer 13 becomes sufficiently large.

In steps c and d, the photoresist pattern 14
Using as a mask, the silicon nitride film 12a and the thin silicon oxide films 11a and 11c surrounding the film are etched away using a hydrofluoric acid solution, thereby selectively exposing a portion of the silicon substrate 10 and the P ⁺ layer 13. As a result, the silicon oxide film 11a, except for part of the silicon substrate 10 and the P ⁺ layer 13,
11b, 11c and a silicon nitride film 12.

In step e, the substrate silicon 10 and the
On a part of the P ⁺ layer 13, an N-type epitaxial layer 15 is formed with a thickness of 5000~
Selectively grow to about 7000 Å. The growth conditions were as follows: dichlorosilane (SiH ₂ Cl ₂ ) was used as the reaction gas, growth rate was 0.5-1.0 μm/min, and growth temperature was 1050-1050 μm/min.
The temperature is about 1100℃ and the pressure during growth is about 80Torr. As a result, the N-type epitaxial layer 15 selectively grows only on the exposed silicon surface.

In step f, using the silicon oxide film 11b and the silicon nitride film 12 as masks, an N ⁺ layer 15a, which is a high concentration N type emitter region, is formed in the N type epitaxial layer 15 by ion implantation at an implantation energy of 40 KeV and a dose. After implanting arsenic ions at an amount of about 6×10 ¹⁵ cm ^-2 , the
Formed by diffusion at temperatures of ~1000°C. Next, N
A P-type base region is formed below in the type epitaxial layer or on top of the substrate silicon 10.
The P ^- layer 16 is formed by implanting boron ions using an ion implantation method at an implantation energy of 140 to 160 KeV and a dose of about 1×10 ¹³ cm ^-2 and annealing at a temperature of about 900° C. for 30 minutes in a nitrogen atmosphere. .

As explained above, by using the method of manufacturing a bipolar integrated circuit according to the present invention, there is no need to etch the highly doped silicon, such as the N ⁺ layer 3 in the emitter region in the conventional example shown in FIG. Since this eliminates variations in the pattern dimensions and shape of the emitter region, it is possible to reduce the variations when controlling the emitter dimensions and high frequency characteristics of the transistor. Further, according to the present invention, there are thin silicon oxide films 11a and 11c directly under and around the silicon nitride film 12a to be removed by dry etching, and this serves as a stopper during plasma dry etching of the silicon nitride film 12a. The controllability of the end point of dry etching is also good.

[Brief explanation of drawings]

FIG. 1 is a process cross-sectional view of a device showing a conventional method for forming a bipolar transistor with a mesa structure emitter region, and FIG. 2 is an embodiment of the present invention, in which a bipolar transistor with a mesa structure is formed. FIG. 3 is a cross-sectional view of an element showing a method of forming the element in the order of manufacturing steps. 1, 10...N-type silicon substrate, 2, 13, 1
6...P type base region, 3...N ⁺ layer, 3a, 1
5a...N-type emitter region, 4, 4a, 11a,
11b, 11c... silicon oxide film, 5, 5a,
12, 12a...Silicon nitride film, 6...Polycrystalline silicon film, 7, 14...Photoresist film pattern, 15...N-type epitaxial layer.

Claims (1)

[Claims] 1. A silicon nitride film formed directly or via an oxide film on the surface of a semiconductor substrate is selectively etched into an annular shape to separate it into an inner island portion and an outer portion, and then the silicon nitride film is used as a mask. a step of implanting impurity ions that give a conductivity type opposite to that of the semiconductor substrate into the semiconductor substrate to form a predetermined region; and a step of implanting a silicon nitride film remaining in the inner island-like portion or a step of removing the film and a silicon oxide film immediately below the semiconductor substrate to expose the surface of the semiconductor substrate; a step of selectively forming an epitaxial layer of the same conductivity type on the exposed semiconductor substrate portion; A method for manufacturing a semiconductor device, comprising the step of converting a lower part of the layer or a top portion of the semiconductor substrate into a layer of an opposite conductivity type.