JPH02278920A - Analog-digital conversion circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption and noise by applying 3rd integration integrating a reference voltage with the same polarity as an unknown input voltage) and using a different integration resistor from those of 2nd and 3rd integration processings. CONSTITUTION:Integration is applied to an unknown input voltage fed to an input terminal 1 by using an integration resistor 6 for a prescribed time Tx and the charge stored in an integration capacitor 9 is discharged till a level discrimination comparator 11 is inverted by using a reference voltage 2 of the inverse polarity of the unknown input voltage. When a timing difference T3 exists between an output of the comparator 11 and a clock 103 at the end of a reference voltage integration timing T1, an input signal changeover circuit 4 switches the integration circuit into the inverse reference voltage 3 and an integration resistor 8 having a resistance of 10 times is used for a period of the succeeding inverting reference voltage integration timing T2 to apply integration till the charge is lost with the inverse reference voltage 3. Thus, since the measuring clock is not increased, the current consumption is less and crosstalk noise due to the measuring clock is reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an integral type analog-to-digital conversion circuit.

[Prior Art] Conventional integral type analog-to-digital conversion circuits perform analog-to-digital conversion by integrating an unknown input voltage and integrating a reference voltage, like a double analog-to-digital conversion circuit.

[Problem M to be solved by the invention] However, in the conventional technology described above, in order to increase the measurement resolution by one order of magnitude, the clock used for conversion must be increased, which increases power consumption and has poor noise resistance. It has the problem of becoming.

The present invention solves these problems.

[Means for Solving the Problems] The analog-to-digital conversion circuit of the present invention includes a first integral that integrates an unknown input voltage, a second integral that integrates a reference voltage of opposite polarity to the unknown input voltage, and A third integration is performed to integrate a reference voltage having the same polarity as the input voltage, and the second integration and the third integration use different integrating resistors.

[Function] According to the above configuration of the present invention, at the same time as measuring the analog-to-digital conversion in the second integration, the time from the comparator judgment of the end of the second integration to the measurement clock is determined, and the third The measurement result is corrected by performing the integration.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram showing its operation.

In the figure, input terminal 1 is applied with an unknown voltage, input terminal 2 is applied with a reference voltage, input terminal 3 is applied with a reverse reference voltage of opposite polarity to the reference voltage, and input signal switching circuit 4 performs analog-to-digital conversion operation. Accordingly, one of input terminals 1, 2, and 3 is selected.

The gain changeover switch 5 and the integration resistor 6 change the integration multiplier at the reference voltage integration timing T1, and the gain changeover switch 7 and the integration resistance 8 set to 10 times change the integration multiplier at the inverse reference voltage integration timing T2. It is used to switch.

The basic integration circuit includes the integration resistors 6 and 8, an integration capacitor 9, an integrator 10, and a level determination comparator 1.
1, the output 102 of the level judgment comparator 11 is connected to the flip-flop 13, and the control signal 1 is connected to the flip-flop 13.
04 is being created.

The basic tally 105 is constituted by a clock 103 and a control signal 104 in the control gate 14, and the correction clock 105 is measured in the basic counter 17.

The correction clock 106 is configured by a signal of opposite polarity of the clock 103 and the control signal 104 at the control gate 15.
Perform correction measurements at .

In the correction measurement, the correction clock 106 is connected to the countdown of the basic counter 16, and the output of the basic counter 16 is connected to the countdown of the basic counter 17. When even one basic counter 16 counts down, the basic counter 17 starts counting down. The lowering is done.

The unknown input voltage applied to the input terminal 1 undergoes Tx integration for a certain period of time, and charges are stored in the integration capacitor 9. The charge stored in the integrating capacitor 9 is discharged using the reference voltage 2 and the reverse reference voltage 3 during the integration period Ts until the level judgment comparator 11 is inverted.The integrator output 101 at this time is shown in the timing diagram. .

Comparator 1 at the end of reference voltage integration timing T1
1 and the clock 103, the input signal switching circuit 4 switches the integrating circuit to the reverse reference voltage of the input terminal 3 and performs the reverse reference voltage integration timing T2.

When the reverse reference integration timing T2 is performed, that is, when the timing T4 exists between the comparator 11 and the clock 103, the integrator 10 inputs the input terminal 2 during the T3 period.
This means that the reference voltage of is extra integrated, and charge is accumulated in the integrating capacitor 9.

During the subsequent reverse reference voltage integration timing T2, the correction clock 106 obtained by performing integration until the charge disappears with the reverse reference voltage using the 10 times integrating resistor 8 is on the extra side at the reference integration timing T1. This corresponds to 10 times the integrated period T3, and analog-to-digital conversion is achieved by subtracting the number of corrected clocks found at the inverse standard integration timing T2 from the value 10 times the result found at the standard integration timing T1°. can.

[Effects of the Invention] As described above, according to the invention, the measurement clock can be adjusted by integrating the charges integrated over the remaining minute in the second integration with an integration multiplier of 10 times in the subsequent third integration. Measurement resolution can be increased without increasing the resolution. In addition, since the measurement clock is not increased, current consumption is low, noise from the measurement clock, etc. can be reduced, and as is clear from this example, the conversion time required for analog-to-digital conversion can be significantly shortened. has.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1 Unknown input voltage input terminal 2 Reference voltage input terminal 3 Reverse reference voltage input terminal 4 Human signal switching circuit 5.7 Gain switching switch 6.8 Reference integrating resistor 9 Integrating capacitor 10 Integrator 11 Level judgment comparator 12 Clock input terminal 13 Flip-flop 14.15 Control gate 16.17 Basic counter FIG. 2 shows tie 101 in one embodiment of the invention.
Integrator output 102 Comparator output 103 Basic clock 104 Control signal 105 Basic clock 106 Correction clocking diagram. Applicant Shiojiri Kogyo Co., Ltd. Representative Patent Attorney Kisanbe Meiki (and 1 other person)

Claims (1)

[Claims] In the integral type analog-to-digital conversion circuit, the integrator integrates an unknown input voltage, a first integral integrates a reference voltage having the opposite polarity to the unknown input voltage, and a second integral integrates a reference voltage having the same polarity as the unknown input voltage. An analog-to-digital conversion circuit, characterized in that a third integration is performed to integrate a reference voltage, and the second integration and the third integration use different integration resistors.