JPH02279072A - Horizontal afc circuit - Google Patents

Abstract

PURPOSE:To attain the improvement of noise resistance and to reduce a synchronizing lock time simultaneously by using an AND output of two horizontal synchronization detection circuits with different sensitivity to switch the gate operation of a horizontal AFC circuit. CONSTITUTION:A 1st horizontal synchronization detection circuit 12 with low detection sensitivity and a 2nd horizontal synchronization detection circuit 13 with high detection sensitivity are provided and a gate pulse is controlled with an AND output of detection outputs of both the circuits. When a phase of a horizontal synchronizing signal is disturbed even slightly, phase disturbance is detected from the AND gate from the output of the 2nd horizontal synchronization detection circuit 13. Moreover, the 1st horizontal synchronization detection circuit 12 holds the detection output with coincident phase against noise for a short period caused at the special reproduction of a VTR and the 2nd horizontal synchronization detection circuit 13 detects phase disturbance. When the noise with a short period is finished, since the and horizontal synchronization detection circuit 13 generates a detection output of phase coincidence immediately, the detection output of the phase coincidence is obtained from the AND gate. Thus, the synchronizing lock time is reduced and the noise resistance is improved.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a horizontal AFC circuit for a television receiver, and in particular to a horizontal AFC circuit that reduces AFC pull-in time and improves noise resistance. It is related to.

(B) Prior Art It is known that horizontal AFC circuits malfunction due to noise in video signals that occurs when an electric field is weak.

As a countermeasure, AFC operation is performed only near the horizontal synchronization signal in the video signal, and AF is not performed during other periods.
A method of prohibiting the C operation is known. Figure 2 is a circuit diagram showing such a horizontal AFC circuit, which includes a gate circuit (2) that gates the horizontal synchronizing signal from the input terminal (1) according to a control signal, and an output signal of the gate circuit (2). A phase comparison circuit (3) that compares the phase between and the flyback pulse.
, a horizontal oscillation circuit (4) whose oscillation is controlled according to the comparison output of the phase comparison circuit (3), and the horizontal oscillation circuit (4).
a horizontal countdown circuit (5) that frequency-divides the oscillation output of the horizontal output circuit (6); and a horizontal synchronization detection circuit (4) that performs a phase comparison between the flyback pulse obtained from the deflection coil (7) and the horizontal synchronization signal. 8).

In FIG. 2, the oscillation output signal of the horizontal oscillation circuit (4) is divided by the horizontal countdown circuit (5) and the frequency ru
(fst is the horizontal frequency) and is applied to the horizontal output transistors (9) and (10) via the horizontal output circuit (6). Then, a flyback pulse as shown in Fig. 3 (a) is generated from the deflection filter (7), and the horizontal synchronization detection circuit (8) is generated.
) and the phase comparison circuit (3).

Assume now that the phase of the horizontal synchronizing signal applied to the input terminal (1), as shown in FIG. 3(B), matches the phase of the flyback pulse in FIG. 3(A). Then, the detection output of the horizontal synchronization detection circuit (8) becomes rH level, and the output is applied to the horizontal countdown circuit (5). Then, the gate signal shown in FIG. 3(c) is generated from the horizontal countdown circuit (5) in response to the rH level signal, and the gate circuit (2) gates the input horizontal synchronizing signal.

Therefore, the horizontal synchronizing signal and the flyback pulse that have passed through the gate circuit (2) are phase-compared in the phase comparison circuit (3), and the oscillation of the horizontal oscillation circuit (4) is controlled according to the error output.

Therefore, the circuit shown in FIG. 2 can prevent malfunctions caused by noise mixed in periods other than the horizontal synchronization signal.

Next, let us assume that a horizontal synchronizing signal as shown in FIG. 3(d) arrives which is out of phase with the flyback pulse shown in FIG. 3(a). Then, “L” is output from the horizontal synchronization detection circuit (8).
The level detection output is added to the horizontal countdown circuit (5), and from the horizontal countdown circuit (5) as shown in Fig. 3 (*
), the gate signal of rH level is connected to the gate circuit (2
) is applied to Therefore, the horizontal synchronizing signal is applied as it is to the phase comparator circuit (3) without being gated.

Therefore, according to the circuit shown in FIG. 2, even when the phase of the horizontal synchronizing signal is temporarily disturbed, such as when switching channels, the synchronization pull-in time can be shortened.

The horizontal countdown circuit (5) includes a decoder that decodes the output of a built-in frequency divider, and is configured to generate a gate signal by the decoder, and the gate signal can be inhibited by resetting the decoder. I can do it.

(C) Problems to be Solved by the Invention Incidentally, in the circuit of FIG. 2, the sensitivity of the horizontal synchronization detection circuit <8) that determines whether the phase of the horizontal synchronization signal is normal is It is determined according to the time constant of 11). The time constant must be set to a medium value in order to satisfy the contradictory characteristics of improving noise resistance and shortening synchronization pull-in time. However, in this case, there was a problem in that neither of the characteristics could be fully satisfied.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and includes a first horizontal synchronization detection circuit with low sensitivity that performs a phase comparison between a horizontal synchronization signal and a flyback pulse, and A highly sensitive second pulse that performs a phase comparison between the horizontal synchronization signal and the flyback pulse.
a horizontal synchronization detection circuit, an AND gate that takes the detection outputs of the first and second horizontal synchronization detection circuits, a gate signal creation circuit that creates a gate signal according to an output signal of the AND gate, and the gate signal. The present invention is characterized in that it includes a gate circuit that performs a gate operation on the horizontal synchronization signal in response to a gate signal from a generation circuit, and compares the phases of the horizontal synchronization signal and the flyback pulse that have passed through the gate circuit.

(*) Effect According to the present invention, a first horizontal synchronization detection circuit with low detection sensitivity and a second horizontal synchronization detection circuit with high detection sensitivity are provided, and the gate pulse is controlled by the AND output of the detection outputs of both circuits. There is. Therefore, if the phase of the horizontal synchronization signal is even slightly disturbed,
Phase disturbance can be detected from the output of the second horizontal synchronization detection circuit using an AND gate. Furthermore, with respect to short-term noise that occurs during special playback of a VTR, the first horizontal synchronization detection circuit maintains a detection output of phase coincidence, and the second horizontal synchronization detection circuit detects phase disturbance. When the short period of noise ends, the second horizontal synchronization detection circuit immediately generates a phase match detection output, so that in this case as well, a phase match detection output can be immediately obtained from the AND gate.

(f) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention, (12)
is the horizontal synchronization signal from the input terminal (1) and the deflection coil (7
) A first horizontal synchronization detection circuit with low sensitivity performs phase comparison with the flyback pulse from (13), a second horizontal synchronization detection circuit with high sensitivity performs phase comparison between the horizontal synchronization signal and the flyback pulse. , (14) are AND gates that match the detection outputs of the first and second horizontal synchronization detection circuits (12) and (13).

Note that circuit elements in FIG. 1 that are the same as those in FIG. 2 are designated by the same reference numerals, and explanations thereof will be omitted.

First, a case where a horizontal synchronizing signal is applied to the input terminal (1) in a strong electric field will be described. The horizontal synchronization signal from the input terminal (1) is shown in Fig. 4 (A), and the flyback pulse from the deflection filter (7) is shown in Fig. 4 (B). From the first horizontal synchronization detection circuit (12), An HJ level detection output indicating that the two signals are in phase is generated and applied to the AND gate (14). The voltage is applied to the AND gate (15) in the synchronization detection circuit (13), and its output becomes as shown in Fig. 4 (c).
R3-FF (R3-FF is an R-8 type flip-flop circuit) (16) and (17) are set. The horizontal oscillation circuit (4) oscillates at a frequency of 32tH, and the horizontal countdown circuit (5) divides the signal by 1/32 to output a signal at a frequency f8. Therefore, if the outputs of each stage of the frequency divider (not shown) constituting the horizontal countdown circuit (5) are combined, the first and second frequency divided outputs shown in FIG. 4 (d) and (*) can be obtained. We can obtain ≠1 and ≠. The Q output of the first R3-FF (16) is inverted to the "L" level by the signal shown in FIG.
It will look like the figure below. Therefore, the second AND gate (22
) is always at the "L" level as shown in FIG. 4 (g). Therefore, the third AND gate (18) becomes conductive according to the Q output of the second R8-FF (17), and the n-ary counter (19) and the third R8-FF (2
0) is released. Therefore, the second frequency-divided output φ passes through the third AND gate (18) and is counted by the n-ary counter 19). When n pieces of the second frequency division output φ8 are applied to the n-ary counter (19), the Q output becomes rH level and sets the third R8-FF (20). ) is the fourth
As shown in figure (h), the level is <'H.

Therefore, the output of the AND gate (14) also becomes "H" level and is applied to the horizontal countdown circuit (5) as a control signal.Then, the gate pulse shown in Figure 4 (S) is sent from the horizontal countdown circuit (5). occurs and the gate circuit (
2) is applied.

Therefore, even if noise is mixed in during a strong electric field, it is possible to prevent the horizontal AFC circuit from malfunctioning.

Here, the sensitivity of the second horizontal synchronization detection circuit (13) for detecting phase coincidence is determined by the count value n of the n-ary counter (19). Therefore, if the count value n is set to 1 or 2,
Sensitivity can be increased.

Next, suppose that the reception state changes from a strong electric field to a weak electric field. At this time, the horizontal synchronizing signal contains a lot of noise as shown in FIG. 6(a), and the synchronizing signal is distorted. Even if such a horizontal synchronization signal is applied to the second horizontal synchronization detection circuit (13), if an L level signal exists during the flyback pulse period shown in FIG. 2R8-F
Since F(16) and (17) are set, the output of the second horizontal synchronization detection circuit (13) maintains the rH level, so the output of the AND gate (14) is set to the first horizontal synchronization detection circuit. It is determined according to the detection output of (12).

Integrating circuit (
The time constant of 21) is set to be large as described above. Therefore, even in the case of a weak electric field, it is possible to continue applying a signal at the rH level to the AND gate (14), and a gate operation can be performed on the incoming horizontal synchronizing signal.

Generally, even in a weak electric field, the phase of the horizontal synchronizing signal is correct, so it is desirable to perform a gate operation.

Suppose that the electric field becomes even weaker from that state. In this case, it is preferable to stop the synchronization pull-in operation and prepare for synchronization with a newly arriving horizontal synchronization signal. That is,
When the electric field becomes extremely weak, the output of the first horizontal synchronization detection circuit (12) becomes "L" level, and the output of the second horizontal synchronization detection circuit (12) becomes "L" level.
The gate operation can be stopped regardless of the output of 3).

Next, assume that the phase of the horizontal synchronization signal is temporarily disturbed due to channel switching or special playback of a VTR. In this case, when a normal state changes to a disturbed state, it is immediately detected and the gate operation is stopped, and when the disturbed state returns to a normal state, it is immediately detected and the gate operation is resumed. It is desirable that the

First, the operation when the horizontal synchronizing signal changes from a normal state to a disturbed state will be explained using FIG. Figure 5 (a)
Assume that the phase of the horizontal synchronizing signal shown in FIG. 5 (b) is ahead of that of the flyback pulse shown in FIG. Then, the output of the first AND gate (15) becomes rH level when the second horizontal synchronizing signal arrives, as shown in FIG. 5(c), but does not reach level rL.
, remains at the level. On the other hand, 1st R5-FF (16
) has already been reset by the second frequency division output φ shown in Fig. 5 (*), so this state is maintained and its Q
, the output is at the "H" level as shown in FIG. Therefore, the first frequency-divided output - shown in Figure 5(d) is the second frequency-divided output.
When added to the AND gate (22), its output is r H,
level, and the second R8-FF (17) is reset, and its Q and output become <'LJ level as shown in Figure 5 (g).
Simultaneous t: 2nd RS-FF(17)(')Q*output cover' Since it becomes HJ level, the n-ary counter (19) and the 3rd R3-FF(20) are reset. Therefore, the second frequency-divided output φ is not added to the n-ary counter (19), and the Q output of the third R8-FF (20) becomes "L" level.

On the other hand, since the first horizontal synchronization detection circuit (12) has low sensitivity,
rH" level signal continues to be output. Therefore, the second
In response to the detection output (L level) of the horizontal synchronization detection circuit (13), the output of the AND gate (14) becomes "L" level and is applied to the horizontal countdown circuit (5). Then,
A gate signal that continues at the rH level as shown in FIG. 5(H) is generated from the horizontal countdown circuit (5) and is applied to the gate circuit (2).

Therefore, according to the circuit shown in FIG. 1, the gate operation can be stopped if the phase of the incoming horizontal synchronizing signal is disturbed even by one period.

Next, assume that the above-mentioned disordered state is switched to a normal state. However, in this case, it is assumed that the noise period is not very long and the first horizontal synchronization detection circuit (12) continues to detect the rH level indicating normality. When the horizontal synchronization signal and the flyback pulse start to match in phase, the first and second R8-FF
(16) and (17) are set, and the second frequency division output φ,
is passed through the third AND gate (18) to the n-ary counter (1
9) will be counted. Therefore, by reducing the count value n, the Q output of the third R5-FF (20) can be immediately inverted to the rH level.

Therefore, in this case as well, the horizontal countdown circuit (5) can be driven by the detection output of the highly sensitive second horizontal synchronization detection circuit (13), and the gate operation can be restarted immediately.

In Fig. 1, the second horizontal synchronization detection circuit (13) is configured with a digital circuit, and the sensitivity is determined by the counted value of the counter. The sensitivity may be determined according to a constant.

In FIG. 1, immediately after the power is turned on, the phase relationship between the horizontal synchronizing signal and the flyback pulse is extremely disturbed. At this time, depending on the timing of the two signals, the output of the second horizontal synchronization detection circuit (13) may accidentally reach the rH level, but the actual phase relationship is still disturbed.

At this time, the output of the first horizontal synchronization detection circuit (12) is at rL level until the power supply stabilizes, and only after stabilization is rL.
It becomes possible to output H level. Therefore, the gate operation is performed after the power is turned on, and it is possible to prevent synchronization from taking a long time.

(G) Effects of the Invention As described above, according to the present invention, the gate operation of the horizontal AFC circuit is switched by the AND output of two horizontal synchronization detection circuits with different sensitivities, thereby improving noise resistance and synchronization. At the same time, the retraction time can be shortened. Therefore, flyback pulses can be stably generated even if the phase of the horizontal synchronizing signal is disturbed, especially during switching or special reproduction of a VTR.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a conventional horizontal AFC circuit, and Figs. 3 (A) to (E) are waveforms for explaining Fig. 2. Figures 4(A) to 4(S) are waveform diagrams for explaining Figure 1, and Figure 5(
A) to (H) are waveform diagrams for explaining FIG. 1, and FIGS. 6A and 6B are waveform diagrams for explaining FIG. (2)...Gate circuit, (3)...Phase comparison circuit, (4)...Horizontal oscillation circuit, (5)...Horizontal countdown circuit, (12)...First horizontal synchronization detection Circuit, (13)...Second horizontal synchronization detection circuit, (14
)...and gate.

Claims (2)

[Claims] (1) A first horizontal synchronization detection circuit with low sensitivity that performs phase comparison between the horizontal synchronization signal and the flyback pulse, and a second horizontal synchronization detection circuit with high sensitivity that performs phase comparison between the horizontal synchronization signal and the flyback pulse. a circuit; an AND gate that ANDs detection outputs of the first and second horizontal synchronization detection circuits; a gate signal generation circuit that generates a gate signal according to an output signal of the AND gate; A horizontal AFC circuit comprising: a gate circuit that performs a gate operation on the horizontal synchronization signal in response to a gate signal of the horizontal synchronization signal; (2) a phase comparison circuit that performs a phase comparison between the horizontal synchronization signal obtained from the gate circuit and the flyback pulse; a horizontal oscillation circuit that oscillates according to the output signal of the phase comparison circuit; and oscillation of the horizontal oscillation circuit. 2. The horizontal AFC circuit according to claim 1, further comprising: a horizontal countdown circuit that divides the frequency of an output signal, and wherein the horizontal countdown circuit is used as the gate signal generation circuit.