JPH02280210A - Microcomputer - Google Patents

Abstract

PURPOSE:To guarantee a high-speed operation frequency even at the time of a low voltage operation by supplying a clock from a clock mask circuit to a circuit in which the operation frequency is lowered the most at the time of the low voltage operation. CONSTITUTION:When a power source voltage is low a high level is inputted to a terminal 8 for detecting a low voltage. A control signal 62 is a control signal to control the circuit to lower the operation frequency at the time of the low voltage of a data transfer to a peripheral circuit unit 2, etc., and when the control signal 62 is generated by a CPU 1, an edge detecting circuit 6 detects the rise of a control signal 61, and a pulse having the width of one clock is generated. When the terminal 8 is at the high level, the pulse generated by the edge detecting circuit 6 is inputted as a clock mask permitting signal 61 to a clock masking circuit unit 4. The clock masking circuit unit 4 masks a clock 50 generated by a generator 3 for a time when the clock mask permit ting signal 61 is active, and the clock is supplied as a clock 55 to the CPU and peripheral circuit unit 2. Thus, the operation at the high frequency can be quranteed even at the time of the low voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer that can cope with power supply voltage fluctuations.

[Conventional technology]

-m, since the maximum operating frequency of a microcomputer changes depending on the power supply voltage, when operating at a low voltage, it is guaranteed that the microcomputer can operate at an operating frequency lower than the operating frequency guaranteed when operating at a normal voltage. Therefore, when operating in an operating voltage range ranging from a normal operating voltage to a low voltage, it is necessary to operate at a low operating frequency guaranteed at low voltages. Recently, a method has also been used in which the clock is divided inside the microcomputer to lower the operating frequency without changing the oscillation frequency even during low-voltage operation.

FIG. 5 is a block diagram of a conventional micro combinator which shows an example of the latter type. A register for controlling the frequency division ratio, 50.53 to 55 are clock signals, and 65 is a control signal for controlling the frequency division ratio of the clock.

The register 23 accessible from the CPU 1 is a register that controls the frequency division ratio of the clock, and the control signal 6 that controls the selector 22 according to the data written by the CPU 1.
The 0 oscillator 3 that generates 5 generates a clock 50 and supplies it to the selector 22 and the binary counter 21 . The binary counter 21 frequency-divides the clock 50 to generate clocks 53 and 54 having a plurality of different frequency division ratios, and supplies the clocks 53 and 54 to the selector 22. Here, each clock 53.54 is 1/2
The clock frequency was divided into 1/8. The selector 22 selects the clock 50 and the divided clock 53.5 according to the state of the control signal 65 generated by the frequency division ratio control register 23.
Select one of 4 and set cpui as clock 55
and the peripheral circuit unit 2.

When using a conventional microcomputer at a low voltage, data for selecting a divided clock is written to the frequency division ratio control register 23 by an instruction, and the operating frequency inside the microcomputer is lowered to prevent malfunction. .

FIGS. 6 and 7 show timing charts at low voltage and normal operating voltage, respectively.

When the voltage is low, the operating frequency is lowered regardless of the microcomputer's operation, so the processing power of systems using conventional microcomputers is significantly reduced.

[Problem to be solved by the invention]

The conventional microcomputers mentioned above must operate over a range of operating power supply voltages from low voltages to normal operating voltages, and when operating at low voltages, the internal clock must be divided and used at a lower frequency. Therefore, there is a drawback that the processing ability of the microcomputer is significantly reduced compared to the normal operating voltage, and the ability of the system using the microcomputer is significantly reduced.

The purpose of the present invention is to eliminate such drawbacks, ensure high frequency operation even when the voltage is low, and increase the operating speed of the entire system by masking the clock only when high speed operation is not possible during low voltage operation. An object of the present invention is to provide a microcomputer in which a decrease in performance is minimized.

[Means to solve the problem]

The configuration of the present invention is to detect that the power supply voltage supplied to each of the circuits has become a low voltage in a microcomputer including a CPU, peripheral circuits, and clock generation means for supplying clocks to these circuits. a voltage detection circuit;
a clock mask circuit that temporarily stops supplying the clock when the voltage detection circuit detects a low voltage;
The present invention is characterized in that, by supplying the clock from the clock mask circuit to the circuit whose operating frequency drops the most during low voltage operation among the circuits, a high operating frequency is guaranteed even during low voltage operation.

〔Example〕

Next, the present invention will be explained using the drawings.

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, and FIGS. 2 and 3 are timing charts during low voltage operation and normal operation in FIG. CPU,
2 is a peripheral circuit unit, 3 is an oscillator, 4 is a clock mask unit for masking a clock, 5 is an OR circuit, 6 is an edge detection circuit, 7 is an AND circuit, 8 is a low voltage detection terminal, 50, 51 . 52 is a clock terminal, 61 is a clock mask enable signal, and 62 is a control signal for controlling a circuit that lowers the operating frequency during low voltage operation.

First, a case in which this microcomputer operates with a low power supply voltage will be explained. When the power supply is at a low voltage, a high level is input to the low voltage detection terminal 8. The control signal 62 is a control signal that controls a circuit that lowers the operating frequency at low voltage such as data transfer to the peripheral circuit unit 2. When this control signal 62 is generated by the CPU, edge detection is performed as shown in FIG. Circuit 6 detects the rising edge of control signal 61 and generates a pulse having a width of one clock.

At this time, a pulse having a width of several clocks may be generated.

If this terminal 8 is at a high level, the pulse generated by the edge detection circuit 6 is inputted to the clock mask circuit unit 4 as a clock mask enable signal 61. The clock mask circuit unit 4 masks the clock 50 generated by the oscillator 3 only during the period when the clock mask enable signal is active, and supplies the masked clock 55 to the CPU and the peripheral circuit unit 2.

Further, the peripheral circuit unit 2 having a circuit such as a timer that would cause a malfunction if the clock is masked is directly supplied with the unmasked clock 50 from the oscillator 3. Therefore, when the power supply is at a low voltage, the operating speed is reduced only when the microcomputer performs a time-consuming operation, and the microcomputer operates very efficiently.

Next, we will explain the case where this microcomputer operates at a normal operating voltage. In the case of 0 normal operating voltage, a low level is input to the low voltage operation detection terminal 8. At this time C
Even if the control signal 62 is generated in the PUI, the clock mask enable signal 61 is not generated as shown in FIG. The clock has the same waveform as the generated clock 50.

Therefore, in the case of normal operating voltage, the operating frequency does not decrease at all.

In conventional microcomputers, when the power supply voltage drops by 10%, the operating frequency drops by 5 to 30%, but with the microcomputer of this embodiment, the power supply voltage can be reduced to about 30% at the same oscillation frequency as before. It is possible to lower it.

FIG. 4 is a block diagram of a second embodiment of the present invention. In this embodiment, an OR circuit 5' and a read-only memory (hereinafter referred to as ROM) 9 are used instead of the OR circuit 5 of the first embodiment. ,
A selector 10 is provided, and a selection signal 64 for selecting a combination of control signals 63 is output from the ROM 9. That is,
In this embodiment, the ROM 9 has data for selecting a combination of a plurality of control signals 63 from the CPUI, so that the fluctuation range of the power supply voltage can be varied depending on the user's purpose and method of use. It has become.

Therefore, a circuit that does not satisfy the operating frequency at low voltage when used by the first user may satisfy the operating frequency in the power supply voltage range used by the second user.

In such a case, the first embodiment cannot be said to be efficient, so in the second embodiment, the ROM 9 contains data for selecting one of the plurality of combinations of the control signals 63. Then, the selector 10 selects one of the plurality of combinations of the control signals 63 based on the selection signal 64 generated by the ROM 9 .

When the selected control signal 63 is generated, the edge detection circuit 6 generates a one-clock pulse, and if a high level is input to the low voltage detection terminal 8, it is sent to the clock mask unit 4 as a mask clock enable signal 61. is input. The clock mask unit 4 masks the clock 50 generated by the oscillator 3 according to the tarlock mask enable signal 61, and supplies the masked clock 55 to the CPUI and the peripheral circuit unit 2.

In this way, in the second embodiment, the user can select in which operation the clock is to be masked, so that the system using this microcomputer can be used in any desired power supply voltage range while maintaining a high-speed oscillation frequency. can be operated most efficiently.

〔Effect of the invention〕

As explained above, the present invention has a means for guaranteeing a high-speed operating frequency, so even if the operating frequency is lowered and the operating speed is significantly reduced, the oscillation frequency can be efficiently maintained without changing the oscillation frequency. It can work. Therefore,
By simply connecting a power supply voltage monitoring circuit to the low voltage detection terminal, the user can set the power supply voltage over a wide range and can configure a system that operates efficiently.

The present invention is particularly useful when power supplies with different power supply voltages (AC power supply, dry batteries, car batteries, etc.) are switched and used, or when the power supply voltage decreases over time, such as when using dry batteries. This is effective when storing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the first embodiment of the present invention, FIG.
FIG. 3 is a timing chart explaining the operation of FIG. 1;
FIG. 4 is a block diagram of a second embodiment of the present invention, FIG. 5 is a block diagram of a conventional microcomputer, and FIGS. 6 and 7 are timing charts explaining the operation of FIG. 5. 1.1'...CPU, 2...Peripheral circuit unit, 3
... Oscillator, 4... Clock mask unit, 5゜5'... OR circuit, 6... Edge detection circuit, 7...
・AND circuit, 8...Low voltage detection terminal, 9...R
OM, 10.22... Selector, 21... Binary counter, 23... Control register, 311.
・Clock selection signal, 50.51.52, 53.54・
... Clock signal, 61... Mask permission signal, 62°63... Control signal, 64... Selection signal, 65...
Clock selection signal.

Claims (2)

[Claims] (1) In a microcomputer that includes a CPU, peripheral circuits, and clock generation means for supplying clocks to these circuits, a voltage detection circuit that detects that the power supply voltage supplied to each of the circuits has become a low voltage; , and a clock mask circuit that temporarily stops the supply of the clock when the voltage detection circuit detects a low voltage, and the clock mask circuit is included in the circuit whose operating frequency decreases the most during low voltage operation among the respective circuits. A microcomputer is characterized in that a high-speed operating frequency is guaranteed even during low-voltage operation by supplying a clock from a microcomputer. (2) The microcomputer according to claim (1), wherein the circuit whose operating frequency decreases when the voltage is low operates under conditions selected according to the contents of a read-only memory stored in advance.