JPH02280258A - Dma controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic device using direct memory access (hereinafter referred to as DMA).

[Prior Art] In electronic devices, DM is used for high-speed data exchange between a storage device and a plurality of human output ports (hereinafter referred to as I/O devices), or for multiple program control.
A is widely used.

A device that executes and controls this DMA is called a DMA controller (hereinafter referred to as DMAC).

As a conventional example 1, a DMA system will be described for a case where there are two I/O devices. FIG. 3 shows a case where the data width of the storage device (hereinafter referred to as memory) 302 is 8 bits.
303 is a central processing unit (hereinafter referred to as CPU), and 303 is a DMAC 1 capable of independently controlling DMA of a plurality of channels, such as μPD8237 manufactured by NEC Corporation. 304-1
, 304-2 is an I/O device, and the I/O device 304-1 is, for example, a floppy disk controller.
The main body that enjoys DMA is an IC chip called FDC, such as μPD765 manufactured by NEC Corporation. For example, if the I/O device 304-2 is a communication control device, the memory 30
The main body that enjoys 2 and DMA is an IC chip called MPSC, such as μP07201 manufactured by NEC Corporation. These IC chips are connected to the DMAC3 during DMA.
03 to the memory 302, and when non-DMA, C
It is designed to exchange data with the PU 300 with an 8-bit data width, and is equipped with a DMA request signal terminal. Not limited to these two examples of I/O devices,
Most devices transfer data in bytes. I/O device 304-1.304-2 and memory 30
2 and the CPU 300 are connected to each other by a data bus 305 and an address bus 306. However, in general ■
/O device 304-1.304-2 is address bus 306
Only part of it is used. Furthermore, I/O device 304-1.
Each DMA request signal 307-1 driven by 304-2
．． 307-2 is sent to the DMAC 303, and a bus request signal 309 driven by the DMAC 303 is sent to the CPU 300, and the bus request signal 309 driven by the DMAC 303 is sent to the
The bus request response signal 312 driven by the PU 300 is a DMA
The DMA permission signal 308-1.308-2 driven by the DMAC 303 is sent to the I/O device 304-1.30.
4-2 are each manned.

In order for the I/O device 304-1 to exchange data with the memory 302 using DMA under such a configuration, first the I/O device 304-1 sends a DMA request signal 30.
7-1 makes a DMA request to DMAC3O3. In response to this, the DMAC 303 requests the CPU 300 to release the bus using a bus request signal 309 . When the DMAC 303 is notified of bus release by the bus request response signal 312, the DMAC 303
MA permission signal 308-1 notifies I/O device 304-1 of DMA permission. In response to this, the I/O device 304-1 starts DMA.

In DMA, first DMAC303 is address bus 3.
The reference address for the memory 302 is output to 06. After that, depending on whether the memory 302 is written or read, in the former case, the I/O is sent to the data bus 305.
After the device 304-1 outputs the data to be written to the memory 302, the memory write signal 3/O is activated, and in the latter case, the memory read signal 311 is activated.

When the memory write signal 3/O is activated, the memory 302 writes the data on the data bus 305 to the address referenced by the address bus 306.

Furthermore, when the memory read signal 311 is activated, the data at the address referenced by the address bus 306 is output to the data bus 305. This data is the I/O device 30
4-1.

In this way, data is exchanged between the I/O device 304-1 and the memory 302, but a common DMAC 30 is also used for DMA between the I/O device 304-2 and the storage device 302.
3 is similarly performed. In the above explanation, I/O
Although we have described the case where there are two devices, there are a total of four DMAC33s.
It is possible to independently control DMA of about 100 I/O devices.

[Problem to be solved by the invention] FIG. 4 shows a DMA system as a second conventional example.

For example, the CPU 401 is MC6800 manufactured by Motorola, USA.
There is 0, and the data width is 16 bits. Therefore, the data width of the memory 402 is also 16 bits. Therefore, the data bus is an 8-bit lower data bus 405-
It consists of a 1 and 8 bit upper data bus 405-2. The memory 402 is a memory block 402-1.40
The memory block 402-1 is connected to the lower data bus 405-1 and allocated as an odd address, and the memory block 402-2 is connected to the upper data bus 405.
-2 and allocated as an even address. On the other hand I
The /O device 404-1.404-2 has a data width of 8 bits, and has an upper data bus 405-1 and a lower data bus 4.
In this example, it is connected to the lower data bus 405-1. Also, memory 40
2 and 1/O device 404-1 or I/O device 404-
A bidirectional bus buffer 414 is provided to enable DMA between 2 and 2 to be performed on any address in the memory 402. The internal configuration of bidirectional bus buffer 414 is shown in FIG.

It consists of two gates 501-1.501-2 and a three-state buffer 502-1.502-2. A signal 503 indicating DMA, a memory read signal 504, a memory write signal 505, and an address generating means 506 are connected to the gates 501-1 and 501-2. game)
DMA by combination of 501-1 and 501-2 inputs
When the memory reference address is an even number, that is, the address generating means 506
When is 0 and (1) is a memory read, three-state buffer 502-2 is enabled and transmits data on data bus 405-2 to data bus 405-1. In addition, (2) during memory write, the three-state buffer 502-1 is enabled and the data on the data bus 405-1 is transmitted to the data bus 405-2.

DMA at odd addresses can be performed without using bidirectional bus buffer 414 because data bus 405-1 directly connects memory 402 and I/O device 404-1 or I/O device 404-2. Bidirectional bus buffer 414 is therefore de-enabled.

By the way, in a 32-bit system where the data bus width has been greatly expanded, the CPU, such as the MC68 manufactured by Motorola in the United States,
020 and the like are extremely flexible in terms of memory data bus width, making it possible to allocate consecutive reference addresses to memories with data widths of 8 bits, 16 bits, and 32 bits.

Therefore, several memories with different data widths can exist in the system. This also applies to I/O devices. In order to satisfy the DMA execution environment using the same concept as the above-mentioned conventional method in such a CPU-based system, a complicated external bus control circuit is required.

Furthermore, although recent personal computers and the like are designed to implement additional functions using expansion boards, it is not known at the time of factory shipment how many expansion boards that require DMA will be used. On the other hand, in the conventional configuration using DMAC, the number of DMA channels is fixed, so the number of expansion boards that perform DMA is limited, or conversely, if the number of expansion boards that perform DMA is small, DM
AC becomes redundant, which causes cost increase.

In view of these problems, the purpose of the present invention is to: 1) eliminate the need for a complex external bus control circuit; 2) enable DMA between I/O devices and memories with various data widths; The objective is to realize a low-cost system that can be easily expanded.

゛[i! Means for Solving the Problem] The present invention provides a plurality of bidirectional bus buffers within the same chip, a control means for the plurality of bidirectional bus buffers,
It includes external bus acquisition means, address generation means for the external storage device, and counting means for counting the number of data transfers, and includes a data width of the storage device and an external! The present invention is characterized in that even when the data widths of the /O devices are different, DMA between the storage device and the external I/O device can be executed without using an external bus control device or the like. means for externally controlling a plurality of bidirectional bus buffers; when the DMA controller is not executing DMA, a CPU connected to an external bus controls the plurality of bidirectional bus buffers inside the DMA controller; The present invention is characterized in that data can be read and written to the external I/O device via a bus buffer, and the present invention further includes a bus authorization signal input pin and a bus authorization output bin, A feature is that a plurality of bus masters including the DMA controller can be placed on an external bus.

[Embodiment] The DMAC of the present invention has ■ data bus terminals connected to memory and CP.
It is separated into those connected to U and those connected to external I/O devices. ■One DMA controller is also used for each external I/O device. ■When used in a system,
It is easy to add the DMA controller and external I/O devices.

■For DMACs that are not performing DMA, the CPU
It has the feature that it can be used as a data bus buffer when reading and writing data to an external I/O device attached to the AC. The following is the DMA of the present invention
C will be explained in detail.

FIG. 1 is an internal block diagram of a DMAC according to the present invention. /O0-1 to /O0-4 are 8-bit data buses, respectively, and are connected to buses on the CPU and storage device sides (not shown). Below, these are UU Babas 0M bus, LM bus
I'll call you Babas LL Babas. /O1-1. /
O12 is an 8-bit data bus, and I
/O Connected to the device side bus. However, if the data width of the I/O device is 8 bits, only /O1-1 is connected. Also, if the data width of the I/O device is 16 bits or 32 bits, /O1-1. /O1-2 are both connected.

118 is a control register, which indicates the direction of data transfer during DMA, ie, whether data is transferred from the I/O device to the memory or vice versa, from the memory to the I/O device, as shown in FIG. 1A. Information and information as to whether the data transfer unit per DMA cycle is a byte, a word, or a longword are set by the CPU. Nao I
If the data width of the /O device is 8 bits, it is a byte, if it is 16 bits, it is a word, and if it is 32 bits, it is a longword. Furthermore, information on whether to issue a DMA end interrupt request and information on whether to permit DMA are also set. The information representing this data transfer unit is the DMA signal S.
1 signal/O2-1. The memory is notified by SO signal /O2-2. /O3 is an interrupt request signal that notifies the CPU of the end of DMA. /O4 is address bus. The first memory response signal 123 and the second memory response signal 124 are signals driven by the memory and indicate that reading or writing in the memory has been completed, and also indicate whether the data width of the memory is 8 bits, 16 bits, or 32 bits. The combination of signals shown in FIG. 1B serves to notify this DMAC of whether the

/O5 is an address strobe signal which is output during DMA and indicates the start of DMA. Also, in non-DMA mode (hereinafter referred to as idle mode), it becomes an input and indicates the start of a CPU bus cycle. /O6 is a memory read signal. /O7 is a memory write signal. /O8 is a bus acquisition request signal. /O9 is a bus use permission manual signal, 1/O is a bus use permission output signal, and these two signals are daisy-chained and used to serially connect another bus master including the DMAC of the present invention (not shown). . Daisy in the DMAC (not shown)
If the control unit decides to activate this bus use permission output signal 1/O only "when the bus use permission input signal /O9 becomes active while the bus acquisition request /O8 is not active", multiple Even if requests for bus acquisition occur simultaneously between bus masters, only one bus master can be given the right to acquire the bus. In other words, each bus master and the DMC recognize that they have received the right to acquire the bus when their own bus use permission manual signal becomes active and their bus use permission output signal becomes non-active.

111 is a data bus switching unit external control signal, 112 is a DMA request signal manually input from the I/O device, and 115 is an I/O device.
DMA response signal of /O device, 116 indicates that DMAC is DMA
The CPU indicates that it is being executed.

and a bus permission response signal to be recognized by other bus masters including the DMAC of the present invention (not shown). The role of the data bus switching unit is 131 in Figure C, 132 in Figure 1, iaa in Figure 1 E, 134 in Figure 1 F, 135 in Figure 1 G, and 1 in Figure 1 G during DMA and idle mode. According to 136 in FIG. H, 137 in FIG. 1, and 138 in FIG. /O1-2 is connected to four 8-bit buses /O0-1 to /O0-4 on the CPU side.

131 in FIG. 1C to 138 in FIG. 1J describe connections between memory-side buses and I/O device-side buses in various combinations of memories and I/O devices having different data widths. In this case, the 8-bit width memory is UU.
For 16-bit wide memory, UU bus 00-1 and UM bus 00-2, for 32-bit wide memory, UU bus 00-IS UM bus 00-2, L
It is assumed that all of M bus 00-3 and LL bus 00-4 are used. It is also assumed that an 8-bit wide I/O device uses an 8-bit bus 1oi-t, and a 16-bit wide I/O device uses 8-bit buses /O1-1 and /O1-2. In the idle mode, the memory side bus and the I/O device side bus are connected only when the external control signal 111 is active.

Since the other internal blocks are functions that the DMAC should naturally have, their explanation will be omitted.

FIG. 2 shows an application example in which the DMAC described above is used in a system.

The application example is when the data bus width of the CPU 200 and memory 201 is 32 bits, and the DMAC 203-1, 203-2
, an I/O device 202-1 that requires DMA and has a data bus width of 8 bits, and an I/O device 202-2 that requires DMA and has a data bus width of 16 bits.
Indicates the case in which the number is used. I/O device 202-
1 and DMAC203-1 is an 8-bit data bus 2.
04-1, a DMA request signal 205-1, and a DMA response signal 206-1. Similarly, I/O device 202
-2 and DMAC203-2 are two 8-bit data buses 204-2, 204-3, and a DMA request signal 205.
-2, connected by the DMA response signal 206-2. C
The PU 200, DMAC 203-1, 203-2, and memory 201 are interconnected by four 8-bit wide data buses.

If these 8-bit data buses are called UU bus, UM bus, LM bus, LL bus, as in FIG.
U Babasu 0? -1, memory block 209-2 is UM
Babasu 0? -2, the memory block 209-3 is the LM bus 07-3, and the memory block 209-4 is the LL bus 0? -4, respectively.

The memory 201 is referenced by the address bus 208, and the address 4n is stored in the storage area in the memory block 209-1, and the address 4n+1 is stored in the memory block 209-2.
In the storage area within, address 4n+2 is memory block 20.
Address 4n+3 is allocated to the storage area in memory block 9-3, and address 4n+3 is allocated to the storage area in memory block 209-4. kokote n
is an integer.

In a system with such a configuration, DMAC203-L DM
The AC203-2 is configured by the CPU 200 to prepare for DMA execution by internal control registers, address registers,
A necessary and valid value is set in the counter and the counter is put on standby.

The two I/O devices 202-1 and 202- are independently DM
Since it is possible to receive A, first the /O device 202
-1 receives byte-sized DMA. First, the I/O device 202-1 sends a DMA request signal 205
-1 is activated to indicate this to the DMAC 203-1. In response to this, the DMAC 203-1 activates the bus request signal 211 and requests the CPU 200 to that effect. Note that the bus request signal 211 is sent to two DMACs 203-
1,203-2 is a wired-OR output of the bus request signal. When the CPU 200 recognizes the bus request, the CPU 200 grants permission to use the bus to the DMAC 203-1 when the CPU 200 has finished using the bus.
The bus use permission signal 212 is activated and transmitted to the DMAC 203-1. At this time, as explained in FIG. 1 above, the bus use permission input signal 213 of the DMAC 203-2 is not activated,
Even if C203-2 requests bus acquisition at that time, the request is not granted and is put on hold. In this case, the DMAC 203-2 needs to continue requesting bus acquisition. Next, when DMAC203-1 recognizes that the right to acquire the bus has been granted, D
A DMA cycle by the MAC 203-1 is started.

First, the DMAC 203 - 1 outputs the reference address of the memory 201 to the address bus 208 . At the same time, the DMA response signal 206-1 notifies the I/O device 202-1 that DMA has started. Hereinafter, (1) the case where DMA transfers data from the I/O device 202-1 to the memory 201, and (2) the case where the DMA transfers data from the memory 201 to the I/O device 202-1 will be explained.

(1) DMA from I/O device 202-1 to memory 201
In the case of data transfer to the UU bus 7-1, the DMAC 203-1 activates the memory write signal 214, and then a data bus switching section (not shown) within the DMAC switches the 8-bit bus 204-1 to the UU bus 7-1.
, UM Babas 7-2, LM Babas 7-3, LL Babas 7
- Connect to all 4 buses. Because DMAC20
3-1 is because the data width of the memory 201 cannot be known at this point.

After a certain access time has elapsed, the memory 201 activates a first memory response signal and a second memory response signal (not shown) to indicate that data writing has been completed, and the DMAC 203-1
DMA is terminated. The two memory response signals also serve to indicate the data width of the memory 201 to the DMAC 203-1.

(2) In the case of data transfer from the memory 201 to the I/O device 202-1, the DMAC 203-1 activates the memory read signal 215. After a certain access time has elapsed, the memory 201 activates two memory response signals to notify the DMAC 203-1 that it is ready to read data. As described above, since the two memory response signals also serve to indicate the data width of the memory 201 to the DMAC 203-1, the DMAC 203-1 can recognize the data width of the memory 201 for the first time at this point. 1 Memory 201 as in this example
In the case of a data width of 32 bits, a data bus switching unit (not shown) in the DMAC 203-1 outputs two memory response signals and an 8-bit bus 204 from the reference address to the memory 201.
Determine and connect the memory side bus to be connected to -1. In other words, the reference address to the memory 201 is 4n, which is UU Babasu 0.
? -1,4n+1 address is 0M bus 207-2.4n+2
Is the address LM Babasu 0? Is address -3,4n+3 LL Babasu 0? -4. However, n is an integer. Thereafter, the data is determined and written to the I/O device 202-1 through the connected bus, and the DMA is completed.

Next, a case where the I/O device 202-2 receives word size DMA will be described.

First, the I/O device 202-2 sends a DMA request signal 20
5-2 to indicate this to the DMAC 203-2. In response to this, the DMAC 203-2 requests the CPU 200 to that effect using the bus request signal 211. C.P.
When the U200 recognizes the bus request, it activates the bus use permission input signal 212 of the DMAC 203-1 to grant permission to use the bus when its own bus use is completed.
Inform C203-1. As shown in the explanation of FIG. 1, if the DMAC 203-1 does not request DMA at that time, the bus use permission signal 213 becomes active and the DMA2
03-2 obtains the right to acquire the bus. On the other hand, at that time DMAC
If DMA 203-1 requests DMA, the bus use permission signal 213 will not become active, and DMAC 203-2 will not get the right to acquire the bus, but DMAC 203-1 will get that right. In this case, the rights of DMAC203-2 are D
This is suspended until the MAC 203-1 completes the DMA.

In this case, the DMAC 203-2 needs to continue requesting bus acquisition. Here, the description will be made assuming that the DMAC 203-2 is given the right to acquire the bus. When DMAC23-2 recognizes that the right to acquire the bus has been granted, DMAC
A DMA cycle by 203-2 is started. First, the DMAC 203-2 connects the memory 20 to the address bus 208.
Outputs the reference address of 1. At the same time, the DMA response signal 206
■/O device 202 indicates that DMA has been started by -2.
Notify -2. From then on (1) DMA is I/O device 2
In the case of data transfer from 02-2 to memory 201 and (2
) The case of data transfer from the memory 201 to the /O device 202-1 will be explained.

(1) DMA from I/O device 202-2 to memory 201
In the case of data transfer to the
-1 and LM bus 07-3, and also 8-bit bus 20
4-3 to UM Babas 7-2 and LL Babas 0? Connect to -4. This is because the DMAC 203-2 cannot know the data width of the memory 201 at this point. After a certain access time has elapsed, the memory 201 indicates that the data transfer has been completed by activating two memory response signals without closing the data width of the memory 201.
It notifies C203-2 and ends the DMA.

(2) In the case of data transfer from the memory 201 to the I/O device 202-1, the DMAC 203-2 activates the memory read signal 215. After a certain access time has elapsed, the memory 201 activates two memory responses to notify the DMAC 203-1 that it is ready to read data. The data bus switching unit can determine the data width of the memory 201 for the first time at this point. In this example, the memory 201 is 3
Since the width is 2 bits, when the reference address is 4n, the 8-bit bus 204-2 is connected to the UU bus 07-1, and the 8-bit bus 204-3 is connected to the 0M bus 20? -2. Also, when the address is 4n+2, the 8-bit bus 204-2 is LM
Babasu 0? -3, the 8-bit bus 204-4 is connected to the LL bus 07-4. However, n is an integer. Thereafter, the I/O device 2-2-2 performs writing using the connected bus, and the DMA ends. Furthermore, address 4n+1 and 4
It is assumed that word-sized DMA from address n+3 is not performed.

In addition to the above, if the DMAC of the present invention is used, two memory response signals (not shown) indicating the data width of the memory output during a memory cycle can be used to change the data width to 8 bits when the data width of the memory is 8 bits. an I/O device, and 1
In the case of 6 bits, DMA can be executed with I/O devices with data widths of 8 bits and 16 bits. Furthermore, even if the data width of the I/O device is 32 bits, DMA can be performed with a memory having a data width of 32 bits by additionally using a 16-bit buffer outside the DMAC.

Next, the operation in so-called idle mode when the DMACs 203-1 and 203-2 do not execute DMA will be explained. As shown in FIG. 2, this DMAC is placed between the I/O device and the CPU side bus on the circuit, so the CPU must be able to access the I/O device through the DMAC. Therefore, in the idle mode, when a chip selection signal (not shown) is input, the bus switching section in the DMAC operates to directly connect a specific 8-bit bus of the CPU side bus to the I/O device side bus. That is, in the explanation of Figure 1 I (
Just as memories are connected by specific CPU-side buses depending on their data width, 8-bit wide I/O devices 2
In the DMAC 203-1 used for 02-1, the 8-bit data bus 204-1 is connected to the UU bus 07-1 and 1
DMA used in 6-bit wide I/O device 202-1
In C203-2, the 8-bit data bus 204-2 is U
U bus 07-1 and 8-bit data bus 204-3 are UM bus 0? -2 is directly connected. In this way, the DMAC functions as a bus buffer in idle mode. DMA of the present invention
CPU as a variation of C to reduce the number of terminals
It is also possible to multiplex part of the side data bus with the address bus.

[Effects of the Invention] The degree of freedom in system design has improved because it is possible to flexibly respond to the data width of memory, data width and number of l/OR devices without using a complicated external bus control device. Also D
Since the MAC functions as a bus buffer when not executing DMA, the original bus buffer is no longer necessary. In addition, since the system uses a daisy-chain system to obtain a bus, it can also be applied to a CPU system with a multiprocessor configuration, which has become mainstream in recent EWS and the like.

[Brief explanation of drawings]

FIG. 1 is an internal block diagram of a DMAC as an embodiment of the present invention. FIG. 1A shows the control register 11 in FIG. 1 according to the present invention.
FIG. 1 B is an explanatory diagram of the designation of the data width of the memory by the first memory response signal 123 and the second memory response signal 124 in FIG. 1 according to the present invention. Figure J is
FIG. 1 is a diagram illustrating the specifications of the internal data bus switching unit according to the present invention. FIG. 2 is a diagram showing an application example of the present invention, in which the data bus has a 32-bit configuration. FIG. 3 is a diagram showing an example of the configuration of a conventional CPU system including a DMAC, in which the data bus has an 8-bit configuration. FIG. 4 is a diagram showing an example of the configuration of a conventional CPU system including a DMAC, in which the data bus has a 16-bit configuration. Figure 5 shows the conventional bus buffer 4 used in Figure 4.
14 is an internal configuration diagram. 117...Data bus switching section 118...Control register 120...Address generation section 121...
Timing generation unit 122...Bus acquisition control unit 12
3... First memory response signal 124... Second memory response signal 46... Bus buffer 411...
Memory write signal 412...Memory read signal 4
13...Address AO signal 54...Memory read signal 55...Memory write signal 56...Address AO signal. Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Kanzo Suzumoto et al. Figure 1B (Connection specification between CPU side bus and I/O!s bus) Bus connection diagram during DMA Diagram D During DMA Bus connection (4) Transfer from memory to 170 13 data Figure 1 G Bus connection during DMA 31s AI is bit 1 of memory address tM. AO is bit 0. 1st 1 - Figure H Bus connection during DMA (2) Transfer from Ilo to memory / 33 Figure E Bus connection during DMA Transfer from memory to Ilo Figure 1 Figure F Figure ■ Figure J Figure 1 Figure 3 Figure 2 Figure 4

Claims (3)

[Claims] (1) The same chip includes multiple bidirectional bus buffers, control means for these multiple bidirectional bus buffers, external bus acquisition means, address generation means for an external storage device, and data transfer frequency control means. It includes a counting means for counting, and even if the data width of the storage device and the data width of the external I/O device are different, the storage device and the external I/O device can be connected without using an external bus control device or the like. DM between
A DMA controller characterized by being capable of executing A. (2) A means for externally controlling a plurality of bidirectional bus buffers, and when the DMA controller is not executing DMA, a CPU connected to an external bus controls the plurality of bidirectional bus buffers inside the DMA controller. 2. The DMA controller according to claim 1, wherein the DMA controller is capable of reading and writing data to the external I/O device via a bidirectional bus buffer of the DMA controller. (3) The DMA controller according to claim 1, further comprising a bus authorization signal input pin and a bus authorization output pin, and providing a function of allowing a plurality of bus masters including the DMA controller to be placed on an external bus. .