JPH02280261A - Dma controller - Google Patents

Abstract

PURPOSE:To perform another job by a CPU by using an internal bus by releasing the bus right of the internal bus to the CPU when the speed of the data transfer of an external bus is decelerated in a burst mode and null time exceeding regulated time occurs. CONSTITUTION:An arbitration controller 5 monitors the status of the data transfer of the external bus DB1, and a timer 51 measures a time while a direct memory access controller DMAC 4 owns the bus right and when the null time occurs in the data transfer on the external bus DB1. When the null time exceeds the regulated time (t), a comparison means 52 detects the fact, and control signal enable is outputted from a signal output means 53 to a separation circuit 6. The separation circuit 6 separates a control signal to the DMAC 4 when receiving the control signal enable, and the DMAC 4 releases the occupancy of an internal data bus, and releases the bus right of the internal bus to the CPU 1. Thereby, the CPU 1 can perform another job by using the internal bus DB.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention is directed to a computer system using DMA (die reflex! memory access) that directly exchanges data between a memory device and an external memory device. The present invention relates to a control device, and more particularly to improving the performance of a bus master (CP tJ ) when using DMA in burst mode.

<Prior Art> FIG. 3 is a conceptual diagram of the configuration of a conventional DMA control device that directly transfers data between memory devices.

In the figure, 1 is the CPU that becomes the bus master, 2 is this CPU
a memory device connected to the PUI via an internal data bus DB; 3 an interface controller for an external bus DBI to which an external memory device (not shown) is connected;
4 is connected to the internal data bus DB and controls the DMA.
MA: 7 controllers.

When the DMA controller 4 receives a data transfer request from the interface controller 3, it requests bus ownership from the CPUI. cpui responds to this request by
D transfers bus rights to DMA controller 4, D gains bus rights
The MA controller 4 transfers data between the memory device 2 and the interface controller 3.

Here, the method of releasing the bus every time the above operation is performed is called "cycle still mode", and the method of continuously repeating the above operation until notification of the end of data transfer from the interface controller is called "cycle still mode". It's called "Burst Mode".

<Problems to be Solved by the Invention> In conventional devices with such a configuration, there is a problem that when the cycle still mode is set, the processing cannot keep up if the external bus transfer speed is high, and when the burst mode is set, the external bus transfer speed is too high. There is a problem in that the slower the transfer speed, the lower the performance of the system.

The present invention has been made in view of the above points, and its object is to realize a DMA control device that can improve the performance of a bus master when DMA is used in burst mode.

Means for Solving the Problems> The present invention for solving the problems described above provides a bus master C.
A PU, a memory device connected to the CPU via an internal data bus DB, an interface controller provided between the external bus and the internal data bus, and a direct memory access (DMA) device connected to the internal data bus.
), which monitors the usage status of an external bus between the CPU and the DMA controller, and if the idle time of the external bus is equal to or greater than a predetermined short-term value, It is constructed by providing an architecture controller that releases the bus rights previously owned by the DMA controller to the CPU.

Function> The DMC controller transfers data in burst mode using an internal data bus. In this state, the arbitration controller monitors the usage status of the external bus, and if there is a free time longer than a short-term fixed value, the CPU
give bus rights to

This allows the CPU to perform data transfer and processing using the internal bus, thereby improving performance.

<Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and in FIG. 0, the same parts as those in the device shown in FIG. 3 are denoted by the same reference numerals.

In the figure, 1 is a CPU as a bus master, 2 is a memory device, 3 is an interface controller that controls the interface between the internal bus BS and external bus DB, and 4
is a DMA controller that transfers data between the interface controller 3 and the memory device 2 in burst mode.

Reference numeral 5 denotes an arbitration controller, which is a feature of the apparatus of the present invention, and monitors the usage status of the external bus DBI and controls the bus right.

This arbitration con!・Inside the roller 5,
A timer 51 measures the time when the external bus is vacant (time when it is not in use), and the measured value of the timer 51 is set to a predetermined value (this predetermined value depends on the nature of data transferred using the external bus). , a signal outputting means 53 for outputting a bus permission signal and a control signal enable according to the comparison result of the comparing means 52. Contains.

Reference numeral 6 denotes a disconnection circuit that disconnects the control signal of the DMA controller 4 according to a signal from the arbitration controller 5, and is provided on the control signal/address bus AB connected to the DMA controller 4.

The operation of the device configured in this way will be described next.

FIG. 2 is a time chart showing an example of the operation. Here, it is assumed that data is transferred from the external memory device or the input/output device I10 side to the internal memory device 2 via the external bus DBI.

(a) shows data transferred on the external bus DBI, and for example, the interval between the first word and the second word is '1' time.

The interface controller 3 receives the data transferred via the external bus DB1, and outputs a transmission request RT' to the DMA controller 4 as shown in (b). The DMA controller 4 receives this transmission request,
As shown in (c), the bus right request BRD is output to the arbitration controller 5. Upon receiving this request, the arbitration controller 5 outputs a bus right request to the CPU 1 as shown in (d), and from cput (
Obtain bus permission BG as shown in e).

The arbitration controller 5, which has received the bus right permission BG, outputs the bus right permission n G RN 'T'' to the DMA controller 4 as shown in (f).

In addition, 1) Receives bus ownership BGACK indicating ownership of the bus from M A controller 1 and roller 4 as shown in (g), and confirms that the bus is occupied by DMA for CPU 1. A signal BAK indicating this is returned as shown in (h).

The DMA controller 4 uses the internal bus DB to transfer data to the memory device [1] as shown in (i) while it owns the DMA /< space right.

Here, the arbitration controller 5 monitors the data transfer status of the external bus DBI, and during the period when the DMC controller 4 owns the bus right, there is a time when there is a vacant space in the data transfer on the external bus DBI. The timer 51 measures this. When this free time exceeds a predetermined time, the comparison means 52 detects this and outputs a control signal enable from the signal output means 53 to the disconnection circuit 6.

Upon receiving this control signal enable, the disconnection circuit 6 disconnects the control signal to the DMC controller 4, and disconnects the control signal from the DMC controller 4.
The A controller 4 releases the occupation of the internal data bus,
The bus right of the internal data bus is released to the CPU 1 at the timing shown by arrow j.

The CPU that has obtained bus ownership can use the internal data bus DB to perform other processing until the next data transfer is performed and bus ownership is requested, improving CPU performance. can.

<Effects of the Invention> As described above in detail, according to the present invention, when the data transfer speed of the external bus becomes slow in burst mode and an empty space is detected for a predetermined time or more, bus ownership of the internal bus is taken over. Since it is freed up for the CPU, the CPU can use the internal bus to do other work, improving performance.

[Brief explanation of drawings]

FIG. 1 is a configuration block diagram showing one embodiment of the present invention, and FIG.
The figure is a time chart showing an example of the operation, and FIG. 3 is a conceptual diagram of the configuration of a conventional DMA control device that directly transfers data between memory devices. 1... Bus master (CPU), 2... Memory device 3
...Interface controller 4...DMA controller 5...Arbitration controller 51...Timer 52...Comparison means 53...Signal generation means DB...Internal data bus, DBI...External bus number Diagram Boots 1st run Diagram

Claims (1)

[Claims] A CPU serving as a bus master, a memory device connected to the CPU via an internal data bus, an interface controller provided between an external bus and an internal data bus, and a memory device connected to the internal data bus. and a DMA controller that controls direct memory access (DMA), which monitors the usage status of an external bus between the CPU and the DMA controller, and determines when the external bus is idle for a predetermined period. A DMA control device comprising an arbitration controller that releases the bus right previously owned by the DMA controller to a CPU when the value exceeds a short-term fixed value.