JPH02280262A - Bus access system and bus system - Google Patents

Abstract

PURPOSE:To constitute a system by using devices with different bus specification by defining the system by a state signal transmitted via a prescribed signal line on a bus without fixing the role of each signal line comprising the bus. CONSTITUTION:The state signals representing the bus specification are outputted from bus masters MPU1 and 2 using the bus BUS, and input/output devices I/01-4 on the bus BUS which is used as slaves monitor the signal, and validates an input/output signal only when the bus masters are provided with the same bus specification. Therefore, no collision or contention occurs in the signal even when plural bus masters MPU1 and 2 with different bus specification and the input/output devices I/01-4 are mixed in the same bus BUS. Thereby, it is possible to constitute the system by using the devices with different bus specification, and to easily change an address or data width, etc., and to improve the flexibility and extendability of the system using the bus BUS.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is particularly applicable to a bus access method consisting of a plurality of signal lines, and when configuring a system by combining devices with different bus specifications. This relates to effective technology, such as technology that is effective when configuring a system that mixes a mode in which address signals and data signals are used in time-division multiplexing on one bus, and a mode in which they are used as a single signal. It is.

[Prior Art] Conventionally, in standard buses such as VMEbus and MULTIBUS, specifications such as the number and nature of signal lines, operating protocols, etc. mainly depend on the signal types and operating protocols of the microprocessor used on the bus master board. It is determined based on. For this reason, bus specifications such as access timing and multiplexing of address signals and data signals are unique to each bus (rVMEbus Architecture Manual, published by CQ Publishing, October 20, 1986, etc.).

[Problems to be Solved by the Invention] In the conventional standard bus, multiple signal lines are mainly defined based on the specifications corresponding to the microprocessor that is the bus master.
The specifications of standard buses such as S differ in the number of signals, signal properties, operating protocols, etc.

In a system created using a standard bus such as the one above,
Devices with different specifications cannot be used together on the same bus. In addition, in systems using standard buses such as those mentioned above, when using different types of microprocessors or peripheral LSIs, data signals and address signals must be adjusted to match the bus width and access signals to other bus specifications. This required hardware to be modified to suit.

For this reason, boards and systems with different bus specifications
Even if mechanical specifications such as connectors were standardized to a standard called Euro size.

There was a problem that they could not be electrically connected to each other.

An object of the present invention is to enable a system to be configured using devices with different bus specifications.

Another object of the present invention is to improve the flexibility and expandability of a system using a bus.

The above and other objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In a bus system where a bus consisting of multiple signal lines such as address signals is used as a signal transmission medium, the access method for these signal lines is not fixed, but is defined by signals indicating the status (bus specification), and a bus master is used on the bus. In addition to providing a signal line that indicates the bus specifications of the bus, the slave I/O device connected to the bus is equipped with a decoding circuit that monitors this signal line, and indicates the bus specification status when the bus master board accesses it. A status signal is output, and the input/output device on the slave side recognizes the bus specifications based on this signal, and if the bus specifications are the same as the self, it activates signal lines such as address lines and data lines for the bus. It is something to do.

[Operation] According to the above-mentioned means, the bus master using the bus outputs a status signal indicating the bus specifications, and the slave input/output device on the bus monitors this signal and detects when the bus specifications are the same. Since only input/output signals are enabled, signal collisions and contentions will not occur even if multiple bus masters or input/output devices with different bus specifications coexist on the same bus.

[Embodiment] FIG. 1 shows an embodiment of a bus system according to the present invention. In the same figure, 10a+10b is a CPU board on which master microprocessors MPU-1 and MPU-2, which can be bus masters, are mounted, respectively;
, 20b, 20c.

20d is an input/output board on which input/output devices l101 to l104 such as a memory and an I10 controller are mounted. On these boards, there is an interface I with bus specifications compatible with each MPU and Ilo protocol.
NF-A, INF-B.

INF-C, . . . are installed, and each board is connected via this interface by a common bus BUS whose bus specifications are not specified.

Further, on the CPU boards 10a and 10b, there are status signal generation circuits 5TG-A and 5TG that generate a status signal ST to indicate the bus specifications of the microprocessor on the board.
-B is provided. The common bus BUS is provided with a dedicated signal line on which the status signal ST is carried.

On the other hand, the input/output boards 20a to 2Od that become bus slaves
On the top is signal determining means DEC-A which monitors the status signal ST supplied from the bus master via the common bus BUS and determines whether it matches its own bus specifications.

DEC-B and DEC-C are provided respectively.

FIG. 2 shows an example of the configuration of the input/output boards 20a to 20d.

The signal determination means DEC includes a buffer 21 that receives the status signal ST on the bus, a setter 22 consisting of a register or a dip switch, etc. that holds a code indicating the bus specifications of the input/output device on its own board, and It consists of a comparator 23 that compares the bus specification code and the status signal ST on the bus, and when the two match, it activates the buffers 24a, 24b, 24c, etc. that constitute the interface INF, and connects the common bus BUS. Connect it to the input/output device I10 on its own board.

Note that 25 is a connector.

If, for example, 4 bits are assigned as the status signal ST, there will be 8 types of bus specifications A, like a robe.

B, C...H can be specified.

FIG. 3 shows examples of bus configurations with different specifications.

Of these, (A) shows an example of a bus specification in which the address signal ADDR and data signal DATA are multiplexed on the same signal line, and (B) shows the address signal ADDR and data signal D
An example of a single-signal bus specification in which the ATA and control signals C0NT are placed on dedicated signal lines, and (C) in the same figure shows a bus specification in which part of the address signal is multiplexed with the data signal. An example of each specification is shown below.

Note that in the figure, N0N-CON indicates an unused signal line.

In this embodiment, for example, when a bus master MPU-1 having a type A bus specification accesses an input/output device l101 having a type A bus specification, the CPU board 10
The status signal generating circuit 5TG-A on the bus sends a signal 5T corresponding to the type A specifications to the bus status signal line determined on the bus.
Generates O-3T3 (=0000). Then, the slave input/output board 20a receives its status signals STO~S.
The signal comparator 23 determines T3 and the code (=0000) held in the setting device 22, and if the bus specifications are the same,
Input/output device l1 via bus interface INF-A
Connect 01 and bus. As a result, addresses and access information are supplied to the slave, and data is input and output from the input/output device.

In addition, in the embodiment shown in FIG.
The input/output board 20d, which has type C bus specifications different from those of 0a and 10b, is connected to the common bus BUS, but this is because the input/output board 20cl has the property of operating independently; This is an example of how such a board can be used as a component of a system. CPU with type A or type B bus specifications
If the board 10a or 10b is replaced with a CPU board that has type C bus specifications, it will be possible to convert data with the input/output board 20d and to control the input/output board 20d from the CPU board. Of course.

Furthermore, in order to make it easier to understand, in the embodiment, a system was explained in which a board was a bus master and a board was a slave. Sometimes there are things that have the property of becoming a bus master. When such a board is used, both the status signal generation circuit STG and the signal determination means DEC may be provided on the board.

In the system of the above embodiment, if you want to expand the data width of a certain board, if it is a board with a single signal bus specification, you can change it to one with a multiplexed bus specification and expand the connector in any way. The data width can be expanded without any problems.

This improves the flexibility and expandability of the bus-based system.

The effects obtained from the above examples are as follows.

(1) In a bus consisting of multiple signals, the content of the signal line or the operation protocol is not defined in advance, but is defined by a signal that indicates the specification state of the bus, and when the bus master uses the bus, it indicates the specification state of the bus. The slave input/output device monitors the signal and connects to the bus when the bus specifications are the same, so the signal line of the input/output device is only connected to the bus when it is accessed. , even if systems with different bus specifications coexist on the same bus, no signal collision or contention will occur.

(2) Even if the bus widths of data buses, address buses, etc. are different and cannot be connected using the same connector.

The bus master multiplexes and uses signal lines on the bus.

Since data can be multiplexed by outputting a signal indicating whether the data or address is connected, there is no need to expand the connector to widen the data or address path width.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, the signal indicating the bus usage status (bus specifications) is 4 bits,
The signal line is placed on a predetermined signal line on the bus, but only one signal line is used to carry the signal indicating the specification status of the bus, and when the microprocessor wants to obtain bus rights, it sends a serial signal with a predetermined pattern. The configuration may also be such that the slave-side board recognizes this and connects each signal line to the bus.

In the above explanation, the invention made by the present inventor was mainly explained as being applied to a system in which a CPU board or an I10 board is connected to hardware having a bus such as a backplane, but this invention is not limited thereto. It can be used in general computer systems such as single board computers, personal computers, and other bus-based computers.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, it is possible to configure a system using devices with different bus specifications, and it is also easy to change addresses and data widths, thereby improving the flexibility and expandability of a system using a bus.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a bus system to which the present invention is applied. FIG. 2 is a block diagram showing an embodiment of an input/output device to which the present invention is applied, and FIG. 3 is a diagram showing an example of the configuration of signal lines with different bus specifications to which the invention is applied. 10a, 10b" CPU board, 20a~20d...
・Input/output board, BUS... bus, MPU-1, 2
...Microprocessor, INF-A, B, C...
...Interface, DEC...Signal judgment means, I
lo...Input/output device, 21...Buffer, 22
... Setting device, 23 ... Comparator, 25 ... Connector, 5TO-3T3 ... Status signal.

Claims (1)

[Claims] 1. In a system in which devices with different specifications are connected to each other via a bus consisting of a plurality of signal lines, the role of each signal line constituting the bus is not fixed, and the role of each signal line on the bus is not fixed. A bus access method characterized by being defined by a status signal transmitted via a signal line. 2. Devices having a plurality of different bus specifications can be connected to a common bus, and a device serving as a bus master among the devices includes status signal generating means for outputting a status signal indicating the bus specifications onto the common bus, Further, the slave device is provided with a signal determining means that monitors the status signal on the common bus and activates the input/output signal for the bus when the bus specifications match. bus system. 3. The signal determining means is composed of a setting device that holds information indicating its own bus specifications, and a comparator that compares the information signal held in the setting device and the status signal on the common bus. 3. The bus system according to claim 2, characterized in that: