JPH02280381A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve drain withstand voltage of a transistor by making thicker a drain region than a channel region constructed into a thin film having the same impurity concentration as the channel region and a width less than a depleted maximum distance of the channel region, between the channel region and the drain region. CONSTITUTION:An SiO2 insulating film 12 having a protruded portion is deposited on a single crystal Si substrate 11 at the center of the surface of the same, and there is formed a silicon-on-insulation type MOS transistor 13 comprising a single crystal and having excellent characteristics such as low stray capacitance. Then, a gate electrode 5 is provided on the protruded portion of the film 12 through a gate oxide film 14, and there are located drain and source regions 17 and 18 constituting the transistor 13 on opposite sides of a channel region 16 located under the electrode 15 putting the channel region 16 therebetween. With such arrangement, thickness T1 of the region 16 is defined as T1>=2[epsilonphiF/(qNs)]<0.5> where epsilon is a dielectric constant, F is Fermi energy eV, q coulomb is the amount of basic charges, and Ns is impurity concentration. Further, thickness T2 of the regions 17, 18 expressed as T2>T1 is obtained.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor film device in which a field effect transistor is formed on a semiconductor film formed on an insulating film, and in particular, to improve transistor characteristics. Regarding the semiconductor film placement.

(Prior art) In recent years, a silicon film (SQllll) formed on an insulating film-Y
l, 3i1icot) On In5ulator
) has been developed to form a MOS transistor. The transistor formed on the 801110 is
This device has excellent characteristics such as latch-up free and low stray capacitance. In such transistors, if the SOIgl is formed thinly so that the entire channel region can be depleted especially in the operating state, characteristics such as improved bunch-through resistance and reduced short channel effect can be obtained. known (IEDM, Tecbnical D
iaest, P. 107.1982).

An example of such a transistor is one having a structure as shown in FIG. 5, for example.

Figure 5 shows a MOS type N-type transistor 1? formed on the SOI FJ. FIG. 2 is a cross-sectional view showing the structure of a channel transistor.

In FIG. 5, an insulating film 2 made of 8102 is formed on a silicon layer 1, and on this insulating film 2, a Sol film 3 made of a P-type single crystal silicon film thinned to about several hundred amps is formed. It is formed. A gate electrode 5 is formed on this SO film 3 via a gate oxide film 4, and a source region 6 consisting of an n+ type impurity diffusion region in the Sol film 3 and sandwiching the gate electrode 5. A drain region 7 is formed. These source region 6 and drain region 17
A channel region 8 is formed in the Sol film 3 between the two.

This channel region 8 is completely depleted in the operating state because the SOI film 3 is iuq-formed.

In such a structure, the film thickness of the drain region 7 becomes thinner as the SOTOsO4 film is formed.

This allows train region 7 and channel fr4ii18
The electric field is concentrated near the boundary between the two and becomes a high electric field.

For this reason, the drain current increases dramatically with the train voltage, making drain breakdown more likely. As a result, in order to suppress an increase in drain current, the drain voltage is significantly restricted, resulting in poor characteristics such as a decrease in operating speed.

(Problems to be Solved by the Invention) As described above, in a transistor formed in a thinned SOr film, the drain region and the channel region have been formed to be thinned. Therefore, the electric field concentrates near the boundary between the channel region and the drain region,
The problem was that the drain breakdown voltage decreased by 1G.

Therefore, the present invention has been made in view of the above, and its purpose is to provide a semiconductor film device in which the drain breakdown voltage of a field effect transistor formed in S 01 fltA is improved. be.

[Effects of the Invention] (Means for Solving the Problem) In order to achieve the above object, a source consisting of a pair of high concentration impurity regions provided at a predetermined distance apart in a semiconductor film formed on an insulating film is provided. In a semiconductor film device comprising a channel region and a drain region, and a gate electrode formed on a channel region sandwiched between these fl'i regions via an insulating film, the present invention provides a method for reducing the thickness of the channel region. The train region is formed to be thicker than the channel region, and the width between the channel region and the drain region is equal to or less than the maximum depletion distance, and is equal to or equal to the channel region. The gist of the above is that a region containing impurity II of 8':J degree lower than the train region is provided.

(Function) In the configuration described in (g), the present invention uses the drain region formed thicker than the channel region to alleviate the concentration of electric field in the channel on the drain region side. In addition, a region formed between the channel region and the drain region having an impurity concentration equal to or higher than that of the channel region and less than the impurity concentration of the drain region causes accumulation of holes generated in the drain region and By preventing impurities from entering the channel region, concentration of the electric field in the channel region on one side of the drain region 1 is further relaxed by -Xi.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a sectional view showing the structure of a semiconductor film 1 showing an embodiment of the present invention. Embodiment t shown in the figure is an example in which the present invention was applied to a MOS type N-channel 17-channel transistor formed in an 801 scale.

In FIG. 1, a single crystal silicon substrate 11-1k has a convex portion of SiC>+l! An insulating film 12 made of J is formed, and a Sol film 13 made of P-type single crystal silicon is formed on this insulating film 12.

A gate electrode 15 is formed on the convex portion of the insulating film 12 of the Sol layer 13 with a gate oxide film 14 interposed therebetween. Further, a drain region 17 and a source region 18 made of an impurity diffusion layer are formed in the S○■ film 13 so as to be opposed to each other with the channel region 16 under the gate electrode 15 interposed therebetween.

Furthermore, between the channel region 16 and the drain region 17,
A region 19 is provided so as to be in contact with the drain region 17 .

In such a structure, the thickness T1 of the channel region 16 is set as shown in the following equation.

T1≦2[εφF/(QNS)]' Here, ε is the permittivity, and φF is the Fermi energy (e
V), Q is the basic charge amount of electrons (coulombs), and Ns is the impurity concentration (cm4).

In the above equation, the right side is a value indicating the maximum thickness that can be completely depleted when the channel region 16 is in an operating state (maximum depletion distance). Therefore, by defining the thickness of the channel region 16 in the above equation, the channel region 16 is completely depleted in the operating state. This provides good switching characteristics.

The drain region 17 and source region 18 have a thickness T
2, it is set so that T2 > TI. That is, the drain region 17 is formed thicker than the channel region 16.

This makes it possible to reduce the concentration of electric field in the boundary region between the channel region 16 and the drain region 17, compared to the conventional structure in which the drain region is made thin like the channel region. As a result, the drain voltage increases, causing the drain current to increase rapidly, and the drain breakdown voltage becomes an electric field.

A region 19 provided between the channel region 16 and the drain region 17 has approximately the same impurity concentration as the channel region 16, has the same thickness as the drain region 17, and has a width W.
is set as shown in the following equation.

0<W≦2[εφF/(QNS)]' Thus, the width W of the region 19 is set to be narrower than the maximum width at which the channel region described above can be completely depleted in the operating state. Of course, the boundary between the N-type high 11 degree impurity region forming the drain region 17 and the region 19 in the 5OIIl 113 with a thickness of T2 is as follows.
The drain region II! is the width of W defined by the above equation beyond the boundary where the thickness of the SOI film 13 changes from T1 to T2! Located on the 17th side.

Here, the region M19 as described above is the channel region 16.
and drain ([17) If there is no channel region 17, a thick drain region 17 with a high impurity concentration will be formed in contact with a thin channel region 16 with low impurity am. In such a case, , drain region 11i121
Highly concentrated impurities in the channel region 16 due to thermal diffusion, etc.
It becomes easier to get inside. When the impurity of the drain region 17 invades into the channel region 16, the channel region 16 becomes 77
Since there are nine films, the impurity concentration near the boundary between the drain region 17 and the channel region 16 in the channel region 16 becomes high. This increases the change in impurity distribution on the drain region 17 side of the channel region 16. Therefore, the channel region 1116 and the drain region 17
The electric field tends to concentrate at the boundary between the two, leading to a decrease in drain breakdown voltage.

However, in this embodiment, the channel region 1
A low concentration region 19 equivalent to 6 is the channel region 1tt16.
and the drain region 17. Therefore, even if impurities in the train region 17 diffuse toward the channel region 16 due to thermal diffusion or the like, the impurities remain in one low concentration region and do not spread inside the channel region 16. There will be no more intrusion. As a result, the channel region 16 and the drain region 1
The concentration of the electric field near the boundary with region 7 is alleviated, and the train breakdown voltage is further increased compared to the case where region 19 does not exist.

Also, since the width of one region is set to be narrower than the maximum width that can deplete the entire channel region, the drain region 1e! The holes generated in 17 are in this region 19
It will no longer be accumulated in Therefore, changes in characteristics that would occur if the region Ia19 is formed thick and holes are accumulated will not occur.

Next, a method for manufacturing a semiconductor film device having the structure described above will be described.
This will be explained with reference to the cross-sectional views of the manufacturing process shown in FIGS. 2(a) to (1).

In the manufacturing method shown in FIG. 2, in order to simplify the manufacturing method, one region similar to that formed on the drain region side is also formed on the source region side. In this way, by forming a region similar to the region 19 formed on the drain region side on the source region side, the effects of the embodiments of the present invention are not impaired, and the characteristics are not deteriorated.

First, an insulating film 12 made of SiO2 is deposited to a thickness of about 1.5 .mu.I on a P-type single crystal silicon substrate 111 having a (100) plane orientation by CVD. Subsequently, a resist pattern (not shown) is formed on this insulating film 12, and using this resist pattern as a mask, the insulating film 12 is
Recesses 21 having a depth of about 3000 A are formed at a predetermined distance apart by reactive ion etching (RIE).

After the formation, the resist pattern formed as a mask on the insulating film 12 is removed (FIG. 2(a)).

Next, polycrystalline silicon is deposited on the entire surface to a thickness of about 8000 Å to form a polycrystalline silicon film 22. Subsequently, a protective film 2 made of 5i02 is formed on this polycrystalline silicon film 22.
3 is deposited to a thickness of about 5.00 Å by the CVD method. After that, a beam annealing process is performed by scanning the electron beam 24, and the acceleration energy of the electron beam is set to 12 KaV.
degree.

The beam current is set to approximately 6111Δ. As a result, the polycrystalline silicon film 22 is melted and recrystallized to form a single crystal, thereby forming a single crystal silicon crotch 25 (FIG. 2(b)). Note that in FIG. 2(b), region 26 indicates a melted region of polycrystalline silicon.

Next, the protective film 23 is melted and removed using an aqueous ammonium fluoride solution. Subsequently, the surface of the single crystal silicon film 25 is
It is oxidized by hydrogen combustion oxidation at a temperature of about 1,000° C. to form an oxide film (not shown).

Next up is single crystal silicon F! After a low concentration of P-type impurity is introduced into the single crystal silicon film 25, the oxide film formed on the single crystal silicon film 25 is removed with an ammonium fluoride aqueous solution.

As a result, an 801FA 13 made of P-type single crystal silicon with a thin film on the convex portion of the insulating film 12 is formed. Here, the thickness of the SOT film 13, which becomes the channel region 16 of the convex portion of the insulating film 12, is about 600 mm, and the thickness of the SOT film 13, which becomes the channel region 16 of the convex portion of the insulating film 12, is about 600 mm. The film thickness is approximately 3,600 people (Figure 2 (C)).

Next, a resist pattern (not shown) is formed on SOI IIQ 13 and h-, and using this resist pattern as a mask, 5OillQ13 outside the area where the element is to be formed is removed by RIE. After that, thermal oxidation treatment is performed at a temperature of about 900°C to form a 5iOz film with a thickness of about 200 people.
A gate oxide film 14 is formed on the SOI film 1. At this time, the surface of 5OIII13 is oxidized and SOI
The thickness of the film 13 decreases by about 100A (Fig. 2(d))
.

Next, after depositing a polycrystalline silicon film over the entire surface, a resist pattern (not shown) is formed that is wider by at most 2W (W is defined by the above formula) than the width of the convex portion of the insulating film 12.
is formed, and using this resist pattern as a mask, the deposited polycrystalline silicon film and gate insulating film 14 are removed.
is removed by etching using the RIE method. As a result, a gate electrode 15 made of polycrystalline silicon that is longer than the width of the convex portion of the insulating film 12 is formed (FIG. 2(e)).

Next, phosphorus, which becomes an N-type impurity, is accelerated with an energy of 2
Ions are introduced into the SOI film 13 by implantation under conditions of 00 KeV1 dose m 1 x 10 15 cm −2 . As a result, a drain region 17 and a source region 18 are formed in the Sol film 13 so as to sandwich the gate electrode 15 . At this time, as described above, the length (L) of the gate electrode 15 is longer than the width of the convex part of the insulating film 12 by 2W, so phosphorus ions are not introduced into the SOf film 13 near the convex part of the insulating film 12. .

As a result, a region 19 having the same impurity temperature as the channel region formed in the So IFJl 3 under the gate electrode 15 is self-contained with a maximum width of W between the channel region 16, the drain region 17, and the source region 18. are formed in a consistent manner (FIG. 2(f)).

Next, after forming an insulating film 27 on the entire surface, contact holes are opened in the drain region 17 and source region 18,
An aluminum wiring 28 is formed in this opening, and a MOS type N-channel transistor is formed (FIG. 2(g)).
).

In the transistor manufactured in this manner, since the drain region 17 is formed thicker than the channel region 16, concentration of electric field near the boundary between the channel region 16 and the drain region 17 can be alleviated. can. This increases the drain breakdown voltage. Furthermore, since one low IA region is provided between the channel region 16 and the drain region 17, diffusion of impurities from the drain region 17 to the channel region 16 is prevented, and electric field concentration is further alleviated. It turns out. As a result, the drain breakdown voltage is further increased, and as shown in FIG. 3, the drain voltage at which the drain current increases rapidly is significantly increased compared to the conventional example.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can be implemented. For example, the transistor formed in the Sol film may be a P channel instead of an N channel. Further, the shape of the recess provided in the insulating film formed on the substrate 11 is not limited to the shape shown in FIG.
For example, as shown in FIG. 4, a tapered recess 21 may be formed in the insulating film 12a on the substrate 11.

Further, the impurity concentration of the region 19 may be equal to or higher than that of the channel region and lower than the impurity temperature of the drain region.

[Effects of the Invention rA] As explained above, according to the present invention, the drain region is formed thicker than the thinned channel region, and the impurity concentration between the channel region and the drain region is equal to that of the channel region. However, since the width is formed to be less than the maximum depletion distance of the channel region, concentration of electric field in the channel region on the drain region side can be alleviated. Thereby, the drain resistance 11 of a transistor whose channel region is a semiconductor film formed thinly on an insulating film can be improved.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the structure of a semiconductor film device according to an embodiment of the present invention, FIG. 2 is a process cross-sectional view showing a method of manufacturing the device not shown in FIG. 1, and FIG. Figure 4 is a process cross-sectional view showing another embodiment of the manufacturing method shown in Figure 2, and Figure 5 is an M49 of a semiconductor film device having a conventional Sot structure. FIG. DESCRIPTION OF SYMBOLS 11... Silicon substrate, 12... Absolute #2IIu, 13... Sol film, 14... Gate insulating film, 15... Gate electrode, 16... Channel region, 17... Drain region , 18...source region, 1...low concentration region. Figure 1

Claims (1)

[Claims] A source region and a drain region consisting of a pair of high concentration impurity regions provided a predetermined distance apart in a semiconductor film formed on an insulating film, and a channel region sandwiched between the two regions. and a gate electrode formed through an insulating film, wherein the thickness of the channel region is less than or equal to the maximum depletion distance of the channel region, and the drain region is thicker than the channel region. A region is provided between the channel region and the drain region, the width of which is less than or equal to the maximum depletion distance, and the impurity concentration is equal to or greater than the channel region and is less than or equal to the impurity concentration of the drain region. A semiconductor device characterized by: