JPH02280439A - Data conversion circuit from time division system into packet system using first-in first-out memory - Google Patents

Abstract

PURPOSE:To decrease the capacity of a buffer memory and to attain the efficient packet processing by using a first-in first-out memory, thereby attaining the packet processing sequentially from the line of the buffer memory whose data storage exceeds one packet. CONSTITUTION:A time division multiplex control means 1 selects a data from a time division multiplex bus based on line assignment location information and fetches it to a buffer memory 2 for each line, and a packet selection means 3 monitors the data quantity at every line in the buffer memory 2 to input the data sequentially from a line capable of applying packet processing to a first-in first-out memory 4. Thus, it is possible to read the data from the buffer memory 2 and the packet selection means 3 at the high speed and to allow the first-in first-out memory 4 to receive the data. Thus, the capacity of the buffer memory 2 is reduced and the efficient packet processing is attained.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a device that performs high-speed communication using fixed-length packets and connects a medium-low speed line interface terminal device, etc. via a Haysband to transmit and receive time-division multiplexed data. The purpose is to provide a circuit that can efficiently packetize data and flexibly respond to line additions, etc. By manually separating time division multiplexed data into data for each line based on the allocation position information for each line. a time division multiplex control means; a buffer memory for storing data for each line at an address specified by the allocation position information for each line; and a buffer memory for storing data for each line at an address specified by the allocation position information for each line; packet selection means for monitoring that a certain amount of data has been reached, selecting each line having a data amount that has reached a certain certain amount, and packetizing and reading data for each selected line from the buffer memory; and a first-in, first-out memory for latching, reading and outputting the packetized data from the packet selection means, and packetizing the data corresponding to the accumulated amount of data stored for each line in the buffer memory. The circuit is configured to read and output the packetized data at high speed.

[Industrial application field]

The present invention relates to a device for transmitting and receiving time-division multiplexed data by connecting a medium-low speed line interface terminal device or the like using baseband to a device that performs high-speed communication using fixed-length packets.

[Conventional technology]

FIG. 3 is a diagram showing a circuit configuration of a conventional example. In the figure, 30
-1 to 30-n are first to n-th devices that transmit and receive medium-low speed data, and 31-1 to 30-n are first line interfaces that receive and output medium-low speed data. section to nth line interface section.

Note that 32 is a data line.

Traditionally, medium-low speeds with small amounts of data (for example, 1200 to 96
When accommodating data at a speed of 0.008 PS), communication devices that employ time division multiplexing, which can efficiently accommodate synchronous continuous communication, are often used. That is, when communicating, for example, between a certain first device 30-1 and another certain n-th device 30-n using the time division multiplexing method as shown in FIG. -1 to nth devices 30-n are provided with first line interface section 31-1 to nth line interface section 31-n, and a method is used in which time division multiplexed data is transmitted via data line 32.

However, in recent years, there has been an increase in the number of communication devices capable of efficient communication that uses fixed-length packets in high-speed backbone data communication systems and can transmit large amounts of data at high speed and in batches. For this reason, there is a strong demand for a circuit that can easily packetize time-division multiplex line data and transmit the packetized data onto a communications backbone system.

(Problem to be solved by the invention) Therefore, it is possible to efficiently packetize data for each line of time division multiplexing, transmit the packetized data on the communication backbone system, and flexibly respond to line speeds. You need to be able to do it.

The present invention efficiently packetizes time division multiplexed data,
The purpose is to provide a circuit that can flexibly respond to line additions, etc.

A buffer memory 2 to be stored at a specified address, and monitoring that the amount of data for each line stored in the buffer memory 2 has reached a certain certain amount. a packet selection means 3 for selecting each line and reading out the selected data for each line from the buffer memory 2 by converting it into packets and nodes;
A first-in, first-out memory 4 is provided for latching the packetized data from the packet selection means 3 and then reading and outputting the packetized data, and a first-in, first-out memory 4 for reading out and outputting the packetized data from the packet selection means 3 is provided. The system is configured to determine the line to be converted into packets, and to read and output the packetized data at high speed.

[Means to solve the problem]

In the present invention, as shown in FIG. 1 showing the principle configuration of the present invention, time division multiplex control means receives time division multiplexed data and separates it into data for each line based on allocation position information for each line. 1, and the data for each line is allocated to the position information for each line. [Function] In the present invention, as shown in FIG.
, the data from the time division multiplexed bus is selected based on the line allocation position information and is imported into the buffer memory IJ 2 for each line. The amount of data is monitored and data is sequentially input to the first-in, first-out memory 4 starting from the line whose amount can be packetized.

Therefore, by reading the data from the buffer memory 2 and the packet selection means 3 at high speed and receiving it in the first-in, first-out memory 4, it is possible to reduce the capacity of the buffer memory U2 and to efficiently packetize the data.

〔Example〕

FIG. 2 is a diagram showing a circuit configuration of an embodiment of the present invention.

In the figure, 10 is a transmission time division multiplex switch, 11 is a time division multiplex control section, 12 is a buffer memory, 13 is a buffer memory write control section, and 14 is a buffer memory read control section. Further, 15 is a transmission packet switch, 16 is a channel control section, and 17 is a first-in first-out memory (hereinafter referred to as FiFo memory).

In FIG. 2, three pieces of information, including time division multiplexed data and allocation positions of nine line speeds, are input from the outside to a transmission time division multiplex switch 10 and a time division multiplex control unit 11, respectively. The time division multiplexing control unit 11 transmits a control signal for selecting time division multiplexed data for each line based on the information on the line allocation position and line speed, and controls the time division multiplexing switch 10 and buffer memory writing. Provided to Department 13.

In the transmission time division multiplexing switch 10, the time division multiplexing control section 1
1 generates data for each line to the buffer memory 12, and the buffer write memory control unit 13 generates a write timing signal and a write address signal to the buffer memory 12 for each line. Each occurs. Then, in the buffer memory 12, according to each of the write timing signal and write address from the buffer memory write control section 13,
Write to a predetermined address in the buffer memory January 2 via the transmit time division multiplex switch IO.

In addition, the channel control unit 16 monitors at regular intervals how much data is written in the buffer memory 12 based on the value of the write address for each channel from the buffer memory write control unit 13, When the amount of data stored in the buffer memory 12 for each channel reaches the amount that can be packetized, read line information is provided to the buffer memory read control section 14 and the transmission packet switch 15, respectively. Then, the buffer memory read control unit 14 reads out one packet worth of data on the corresponding line in accordance with the read line information using a read signal faster than the read clock on the time division multiplexed bus and the packet line side. 16 selects the data of the channel according to the line information instructed and sends it to the transmission packet switch 15.

Note that in the transmitting packet switch 15, the buffer memory 1
The line information from the channel control unit 16 is added to one packet of data read from the FIFO memory 17 (hereinafter referred to as the FiFo memory 17). Note that the FiFo memory 17 latches and takes in packet data from the transmission packet switch 15, and sends it out as packet data in accordance with a desired line speed.

That is, in the present invention, in order to make the capacity of the buffer memory as small as possible and to reduce the amount of delay of high-speed data, (1) reading from the buffer memory 12 at high speed,
o Memo January 7 is temporarily written at high speed.

■ Read data from the FiFo memory 17 at high speed according to the desired line speed.

The circuit is configured as follows.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, by using a first-in, first-out memory, packetization can be performed sequentially from a line where the amount of data stored in the buffer memory is one packet or more, and Capacity reduction and efficient packetization can be performed.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a diagram showing a circuit configuration of an embodiment according to the present invention, Figure 3 is a diagram showing the circuit configuration of a conventional example. It is. In the figure, 1 is a time division multiplex control means; 2 is buffer memory, 3 is a packet selection means; 4 is first-in first-out memory; shows. ;- death Conventional example / 10 坏 J 戎 'e ね Tffi Figure 3

Claims (1)

[Scope of Claims] Time division multiplexing control means (1) for inputting time division multiplexed data and separating it into data for each line based on allocation position information for each line; and the data for each line. A buffer memory (
2) and monitoring that the amount of data for each line stored in the buffer memory (2) has reached a certain amount, and selecting each line whose data amount has reached the certain amount. and packet selection means (3) for packetizing and reading data for each line selected from the buffer memory (2).
and a first-in, first-out memory (4) for latching, reading and outputting the packetized data from the packet selection means (3), the data stored in the buffer memory (2) for each line. The line to be packetized is determined according to the accumulated amount of
A data conversion circuit from a time division method to a packet method using a first-in first-out memory, characterized in that the packetized data is read and output at high speed.