JPH0228111U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a connection diagram showing an embodiment of the bias circuit according to this invention, and FIG. 2 is a connection diagram showing a conventional bias circuit. In the figure, D1 is a zener diode, E1 to E7
are terminals, R1 to R7 are resistors, RT1 to RT3
is a posistor, and TR1 and TR2 are field effect transistors. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] a field effect transistor, a gate bias terminal connected to the gate terminal of the field effect transistor, a first resistor connected to one of the gate bias terminals and the other grounded, and the gate bias terminal. a first basic bias circuit comprising a second resistor having one end connected to the field effect transistor, a drain bias terminal connected to the drain terminal of the field effect transistor, and a third resistor connected to the drain bias terminal; A second basic bias circuit which has the same configuration as the first basic bias circuit and includes a gate bias terminal, a fourth resistor, a fifth resistor, a drain bias terminal and a sixth resistor, and a first basic bias circuit. the second of
a POSISTOR having one end connected to the other of the resistors and the other of the fifth resistor of the second basic bias circuit; a Zener diode having one end connected to the other of the POSISTORs and the other terminal thereof being grounded; a seventh resistor connected to the other side of the POSISTOR; a negative power supply terminal connected to the seventh resistor; a third resistor of the first basic bias circuit; and a sixth resistor of the second basic bias circuit. A bias circuit with a positive power supply terminal connected to the terminal and a ground terminal.