JPH0228154U - - Google Patents

Info

Publication number
JPH0228154U
JPH0228154U JP10717088U JP10717088U JPH0228154U JP H0228154 U JPH0228154 U JP H0228154U JP 10717088 U JP10717088 U JP 10717088U JP 10717088 U JP10717088 U JP 10717088U JP H0228154 U JPH0228154 U JP H0228154U
Authority
JP
Japan
Prior art keywords
attenuator
storage device
data corresponding
selected channel
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10717088U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10717088U priority Critical patent/JPH0228154U/ja
Publication of JPH0228154U publication Critical patent/JPH0228154U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Circuits Of Receivers In General (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案を実施したＶＴＲの要部ブロツ
ク図、第２図はその要部の具体的回路図、第３図
は従来の受信装置の要部ブロツク図である。 ３……アンテナ入力端子、５……チユーナ、６
……高周波増幅回路、１６……マイクロコンピユ
ータ、１７……メモリ。 FIG. 1 is a block diagram of the main part of a VTR embodying the present invention, FIG. 2 is a specific circuit diagram of the main part, and FIG. 3 is a block diagram of the main part of a conventional receiving apparatus. 3...Antenna input terminal, 5...Tuner, 6
...High frequency amplifier circuit, 16...Microcomputer, 17...Memory.

Claims (1)

【実用新案登録請求の範囲】 アンテナ入力端子とチユーナの高周波増幅回路
の間に設けられた可変アツテイネータと、 各選局チヤンネルに対応したアツテイネータデ
ータが記憶された記憶装置と、 選局されたチヤンネルに対応するアツテイネー
タデータを前記記憶装置から読出して前記可変ア
ツテイネータに供給する制御回路とを備える受信
装置。[Claims for Utility Model Registration] A variable attenuator provided between an antenna input terminal and a high frequency amplification circuit of a tuner, a storage device storing attenuator data corresponding to each selected channel, and a selected channel. A receiving device comprising: a control circuit that reads attenuator data corresponding to a channel from the storage device and supplies the read attenuator data to the variable attenuator.
JP10717088U 1988-08-12 1988-08-12 Pending JPH0228154U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10717088U JPH0228154U (en) 1988-08-12 1988-08-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10717088U JPH0228154U (en) 1988-08-12 1988-08-12

Publications (1)

Publication Number Publication Date
JPH0228154U true JPH0228154U (en) 1990-02-23

Family

ID=31341341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10717088U Pending JPH0228154U (en) 1988-08-12 1988-08-12

Country Status (1)

Country Link
JP (1) JPH0228154U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4946308A (en) * 1972-09-05 1974-05-02
JPS5437618A (en) * 1977-08-31 1979-03-20 Sony Corp Receiver

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4946308A (en) * 1972-09-05 1974-05-02
JPS5437618A (en) * 1977-08-31 1979-03-20 Sony Corp Receiver

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