JPH02283073A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH02283073A JPH02283073A JP10504789A JP10504789A JPH02283073A JP H02283073 A JPH02283073 A JP H02283073A JP 10504789 A JP10504789 A JP 10504789A JP 10504789 A JP10504789 A JP 10504789A JP H02283073 A JPH02283073 A JP H02283073A
- Authority
- JP
- Japan
- Prior art keywords
- film
- amorphous
- laser annealing
- semiconductor device
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 33
- 238000005224 laser annealing Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 12
- 239000013078 crystal Substances 0.000 description 8
- 239000007790 solid phase Substances 0.000 description 6
- 239000012071 phase Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、非結晶Siをチャネル層とするMO8型トラ
ンジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an MO8 type transistor having a channel layer made of amorphous Si.
[従来の技術]
近年、非結晶Siを使用したMO8型TFT (Thi
n Film 丁ransistors)デバイスが、
液晶を用いた表示用デバイスや一次元のイメージセンサ
デバイスとして、量産されるようになってきた。しかし
、前記表示用デバイスでは、表示すイズの大型化や高精
細化などに対応するため、また、−次元のイメージセン
サデバイスでも、高密度化に対応するため、TPT素子
の電気的特性の向上が要求されている。[Prior art] In recent years, MO8 type TFTs (Th
The device is
They are now being mass-produced as display devices using liquid crystals and one-dimensional image sensor devices. However, in the display devices mentioned above, in order to cope with larger display sizes and higher definition, and also in -dimensional image sensor devices, in order to cope with higher density, the electrical characteristics of TPT elements have to be improved. is required.
TPT素子の電気的特性向上の手段には、チャネル層と
なる非結晶Siのグレインサイズを大きくする低温での
固相成長技術と、レーザアニール技術がある。また、チ
ャネル層の膜厚は薄いほうがTPTの電気的特性がよい
ことも周知の事実である。しかし非結晶Si膜はある程
度厚いほうが、前記固相成長やレーザアニールの時、大
きなグレインが成長することが解っている。従って従来
のTPT素子の製造ではチャネル層として1層の適当な
膜厚の非結晶Si膜を用いていた。Means for improving the electrical characteristics of a TPT element include a low-temperature solid-phase growth technique that increases the grain size of amorphous Si that becomes a channel layer, and a laser annealing technique. It is also a well-known fact that the thinner the channel layer, the better the electrical characteristics of TPT. However, it is known that the thicker the amorphous Si film is to a certain extent, the more large grains will grow during the solid phase growth or laser annealing. Therefore, in the conventional manufacturing of TPT elements, a single layer of amorphous Si film of an appropriate thickness has been used as the channel layer.
[発明が解決しようとする課題]
従来のTPT構造では、チャネル層とソース・ドレイン
領域となる非結晶SL膜は1層で形成されていたため、
レーザアニール技術や固相成長技術の特徴である非結晶
Si膜の粒径の増大が、TPTの電気的特性の向上に十
分には寄与しなかった。[Problems to be solved by the invention] In the conventional TPT structure, the amorphous SL film that becomes the channel layer and source/drain regions is formed in one layer.
The increase in grain size of the amorphous Si film, which is a feature of laser annealing technology and solid phase growth technology, did not sufficiently contribute to improving the electrical characteristics of TPT.
即ち、TPTの電気的特性を向上させるためチャネル層
となる非結晶Si膜の膜厚を薄くしたいという要求と、
前記粒径を増大させるため非結晶Si膜の膜厚をある程
度厚くしたいという要求を同時に満たすことができない
という問題点を有する。In other words, there is a demand to reduce the thickness of the amorphous Si film that becomes the channel layer in order to improve the electrical characteristics of TPT, and
In order to increase the grain size, there is a problem in that it is not possible to simultaneously satisfy the demand for increasing the thickness of the amorphous Si film to a certain extent.
従って本発明はこの様な問題点を解決するもので、その
目的とするところは、チャネル層となる非結晶Si膜が
薄くても結晶粒の大きいTPT素子およびその製造方法
を提供することにある。Therefore, the present invention is intended to solve these problems, and its purpose is to provide a TPT element in which the amorphous Si film serving as the channel layer has large crystal grains even if it is thin, and a method for manufacturing the same. .
[課題を解決するための手段]
本発明において、前記課題を解決するための手段は、
(1)絶縁基板乃至絶縁膜上に、ソースおよびドレイン
となるべき第1の非結晶Si膜と、チャネル層となる第
2の非結晶Si膜と、ゲート絶縁膜と、ゲート電極とか
らなる半導体装置において、該第1の非結晶Si膜の膜
厚が1000Å以上で、且つ該第2の非結晶Si膜の膜
厚が1000Å以下であることを特徴とする。[Means for Solving the Problems] In the present invention, the means for solving the problems are as follows: (1) A first amorphous Si film to be a source and a drain, and a channel are formed on an insulating substrate or an insulating film. In a semiconductor device comprising a second amorphous Si film serving as a layer, a gate insulating film, and a gate electrode, the first amorphous Si film has a thickness of 1000 Å or more, and the second amorphous Si film The film is characterized in that the film thickness is 1000 Å or less.
(2)絶縁基板乃至絶縁膜上に、ソースおよびドレイン
となるべき第1の非結晶Si膜を形成する工程と、次に
チャネル層となる第2の非結晶S1膜を基板全面に形成
する工程と、次に基板全面をレーザアニールする工程と
、次に前記第2の非結晶Si膜を所望のバタンに形成す
る工程と、次にゲート絶縁膜を形成する工程と、次にゲ
ート電極を形成する工程とからなることを特徴とする。(2) A step of forming a first amorphous Si film that will become a source and a drain on an insulating substrate or an insulating film, and a step of forming a second amorphous S1 film that will become a channel layer over the entire surface of the substrate. Then, a step of laser annealing the entire surface of the substrate, a step of forming the second amorphous Si film in a desired pattern, a step of forming a gate insulating film, and a step of forming a gate electrode. It is characterized by comprising the steps of:
(3)前記レーザアニールにおいて、レーザの波長が4
00nm以下であることを特徴とする。(3) In the laser annealing, the wavelength of the laser is 4
It is characterized by having a diameter of 00 nm or less.
(4)前記レーザアニールの代わりに、600±50℃
の温度で3時間以上の熱処理を行うことを特徴とする。(4) Instead of the laser annealing, 600±50°C
It is characterized by performing heat treatment at a temperature of 3 hours or more.
【実施例] 本発明の詳細を実施例により以下に説明する。【Example] The details of the invention will be explained below by way of examples.
第1図および第2図は本発明による実施例を説明するた
めの、TPTの断面図の一部を示している、第1図はレ
ーザアニールや低温での固相成長を行う工程の断面図を
示し、第2図は電極配線まで行ったTPT素子の断面構
造を示している。1 and 2 show a part of a cross-sectional view of TPT for explaining an embodiment according to the present invention. FIG. 1 is a cross-sectional view of a process of performing laser annealing and solid phase growth at a low temperature. FIG. 2 shows the cross-sectional structure of the TPT element including electrode wiring.
第1図において101はガラス基板、102はTPTの
ソース・ドレインとなる第1の非結晶Siであり、10
3はチャネル層となる第2の非結晶Siである。前記第
1の非結晶Siはソース・ドレイン領域に対応してバタ
ンニングされているが、前記第2の非結晶Siは基板全
面に成膜されており、バタンユング前の状態にある。低
温での同相成長やレーザアニールは第1図の状態で行う
。第1の非結晶5iiiiの膜厚は約1000人であり
、第2の非結晶Si膜の膜厚は200〜300人である
。レーザアニルのとき、非結晶Siの膜厚が厚い領域で
は、レーザアニールのエネルギが吸収され易いため、他
の膜厚が薄い領域より高い温度になり、再結晶化も早く
始まる。前記膜厚が薄い領域は再結晶化が遅く始まり、
早く再結晶化された領域の影響を受け、前記第2の非結
晶Si膜の結晶粒径は、最終的には前記第1の非結晶S
i膜がなく第2の非結晶Si膜膜層層場合に比べて大き
くなる。In FIG. 1, 101 is a glass substrate, 102 is a first amorphous Si that becomes the source/drain of TPT, and 10
3 is a second amorphous Si serving as a channel layer. The first amorphous Si is battened corresponding to the source/drain regions, but the second amorphous Si is deposited on the entire surface of the substrate and is in a state before battening. In-phase growth at low temperature and laser annealing are performed under the conditions shown in FIG. The thickness of the first amorphous Si film 5iii is approximately 1000 mm, and the thickness of the second amorphous Si film is 200 to 300 mm. During laser annealing, the energy of the laser annealing is easily absorbed in regions where the amorphous Si film is thick, so the temperature is higher than in other regions where the film thickness is thin, and recrystallization begins earlier. In the region where the film thickness is thin, recrystallization starts slowly,
Under the influence of the early recrystallized region, the crystal grain size of the second amorphous Si film eventually becomes the same as that of the first amorphous Si film.
It is larger than the case where there is no i-film and the second amorphous Si film layer is used.
第3図〜第5図は従来技術によるTPT製造過程の一部
を示したものである。第3図は非結晶5iff302を
基板全面に成膜した状態であり、通常レーザアニールや
固相成長はこの状態で行われる。第4図は第3図に続い
て前記非結晶Si膜が、ソース・ドレインおよびチャネ
ルとなるべき領域にバタンニングされていることを示し
ている(402)。第5図は第4図に続いてゲート絶縁
膜504が形成され、次【こゲート電極505が形成さ
れ、最終的に電極配線507まで形成されているTPT
の断面図を示している。TPTの電気的特性はチャネル
部Siの結晶粒径で決まる。チャネル部Siは、従来技
術では第3図302又は第4図402又は第5図502
であり、本発明では第1図103又は第2図203であ
る。両者チャネル部Siの結晶粒径は、レーザアニール
や同相成長を行うときの素子の断面構造の相違に関係し
ている。即ち第1図と第3図の相違である。3 to 5 show a part of the TPT manufacturing process according to the prior art. FIG. 3 shows a state in which amorphous 5iff 302 is deposited on the entire surface of the substrate, and laser annealing and solid phase growth are normally performed in this state. Continuing from FIG. 3, FIG. 4 shows that the amorphous Si film is slammed into regions that are to become sources, drains, and channels (402). FIG. 5 shows that following FIG. 4, a gate insulating film 504 is formed, then a gate electrode 505 is formed, and finally an electrode wiring 507 is formed.
A cross-sectional view of the is shown. The electrical characteristics of TPT are determined by the crystal grain size of the Si channel portion. In the prior art, the channel portion Si is as shown in FIG. 3 302, FIG. 4 402, or FIG. 5 502.
In the present invention, it is 103 in FIG. 1 or 203 in FIG. 2. The crystal grain size of both channel portions Si is related to the difference in the cross-sectional structure of the device when laser annealing or in-phase growth is performed. That is, this is the difference between FIG. 1 and FIG. 3.
前記チャネル部Siの結晶粒径の相違について、レーザ
アニールについてはすでに前述した通りである。同相成
長の場合は、従来技術の第3図の状態では、非結晶S1
膜302の膜厚が均一のため同相成長がランダムに起こ
るが、本発明による第1図の場合は非結晶Si膜102
が存在する膜厚が厚い領域から結晶成長が始まり、非結
晶5ifi103だけが存在するチャネル領域は、前記
102で始まった結晶成長によって結晶化が進む。した
がってチャネル部Siの最終的な結晶粒径は、本発明に
よる第1図又は第2図のほうが従来技術である第3図な
いし第5図より大きくなる。Regarding the difference in the crystal grain size of the channel portion Si, the laser annealing has already been described above. In the case of in-phase growth, in the state of the prior art shown in FIG.
Since the thickness of the film 302 is uniform, in-phase growth occurs randomly, but in the case of FIG. 1 according to the present invention, the amorphous Si film 102
Crystal growth starts from the thick region where 102 is present, and crystallization progresses in the channel region where only the amorphous 5ifi 103 exists due to the crystal growth that started at 102 above. Therefore, the final crystal grain size of the channel portion Si is larger in FIG. 1 or FIG. 2 according to the present invention than in FIGS. 3 to 5 according to the prior art.
[発明の効果]
本発明によれば、200〜300人程度の薄い非結晶S
i膜でも、レーザアニール技術や固相成長成技術により
、より大きなグレインサイズにすることができ、従って
電気的特性の優れたTPT素子を製造することができる
。[Effect of the invention] According to the present invention, about 200 to 300 thin amorphous S
Even in the case of an i-film, a larger grain size can be obtained using laser annealing technology or solid phase growth technology, and therefore a TPT element with excellent electrical characteristics can be manufactured.
第1図および第2図は本発明によるTPTの断面図。第
3図〜第5図は従来技術によるTPTの断面図。
101.201.301.401 、501 ・ ・
・ガラス基板
102.202.302.402.502・・非結晶5
i
103.203・・・非結晶5i
204.504・・・ゲート絶縁膜
以上
出願人セイコーエプソン株式会社
代理人弁理土鈴木喜三部(他1名)1 and 2 are cross-sectional views of the TPT according to the present invention. 3 to 5 are cross-sectional views of TPT according to the prior art. 101.201.301.401 , 501 ・ ・
・Glass substrate 102.202.302.402.502...Amorphous 5
i 103.203...Amorphous 5i 204.504...Gate insulating film and above Applicant Seiko Epson Corporation Attorney Kizobu Tsuchi Suzuki (and 1 other person)
Claims (4)
となるべき第1の非結晶Si膜と、チャネル層となる第
2の非結晶Si膜と、ゲート絶縁膜と、ゲート電極とか
らなる半導体装置において、該第1の非結晶Si膜の膜
厚が1000Å以上で、且つ該第2の非結晶Si膜の膜
厚が1000Å以下であることを特徴とする半導体装置
。(1) A semiconductor consisting of a first amorphous Si film to serve as a source and a drain, a second amorphous Si film to serve as a channel layer, a gate insulating film, and a gate electrode on an insulating substrate or insulating film. A semiconductor device, wherein the first amorphous Si film has a thickness of 1000 Å or more, and the second amorphous Si film has a thickness of 1000 Å or less.
となるべき第1の非結晶Si膜を形成する工程と、次に
チャネル層となる第2の非結晶Si膜を基板全面に形成
する工程と、次に基板全面をレーザアニールする工程と
、次に前記第2の非結晶Si膜を所望のパタンに形成す
る工程と、次にゲート絶縁膜を形成する工程と、次にゲ
ート電極を形成する工程とからなることを特徴とする半
導体装置の製造方法。(2) A step of forming a first amorphous Si film to become a source and a drain on an insulating substrate or an insulating film, and a step of forming a second amorphous Si film to become a channel layer over the entire surface of the substrate. Next, a step of laser annealing the entire surface of the substrate, a step of forming the second amorphous Si film in a desired pattern, a step of forming a gate insulating film, and a step of forming a gate electrode. A method for manufacturing a semiconductor device, comprising the steps of:
00nm以下であることを特徴とする請求項2記載の半
導体装置の製造方法。(3) In the laser annealing, the wavelength of the laser is 4
3. The method of manufacturing a semiconductor device according to claim 2, wherein the thickness is 00 nm or less.
の温度で3時間以上の熱処理を行うことを特徴とする請
求項2記載の半導体装置の製造方法。(4) Instead of the laser annealing, 600±50°C
3. The method of manufacturing a semiconductor device according to claim 2, wherein the heat treatment is performed at a temperature of 3 hours or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1105047A JP2689596B2 (en) | 1989-04-25 | 1989-04-25 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1105047A JP2689596B2 (en) | 1989-04-25 | 1989-04-25 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02283073A true JPH02283073A (en) | 1990-11-20 |
| JP2689596B2 JP2689596B2 (en) | 1997-12-10 |
Family
ID=14397085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1105047A Expired - Fee Related JP2689596B2 (en) | 1989-04-25 | 1989-04-25 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2689596B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05175504A (en) * | 1991-12-20 | 1993-07-13 | Mitsubishi Electric Corp | Field effect semiconductor device |
| US6025217A (en) * | 1994-11-24 | 2000-02-15 | Sony Corporation | Method of forming polycrystalline semiconductor thin film |
| US6815269B2 (en) * | 2002-05-08 | 2004-11-09 | Nec Lcd Technologies, Ltd. | Thin-film transistor and method for manufacturing the same |
| US7745822B2 (en) | 2003-06-27 | 2010-06-29 | Nec Corporation | Thin film transistor and thin film transistor substrate including a polycrystalline semiconductor thin film having a large heat capacity part and a small heat capacity part |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6239068A (en) * | 1985-08-14 | 1987-02-20 | Sony Corp | Manufacture of semiconductor device |
-
1989
- 1989-04-25 JP JP1105047A patent/JP2689596B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6239068A (en) * | 1985-08-14 | 1987-02-20 | Sony Corp | Manufacture of semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05175504A (en) * | 1991-12-20 | 1993-07-13 | Mitsubishi Electric Corp | Field effect semiconductor device |
| US6025217A (en) * | 1994-11-24 | 2000-02-15 | Sony Corporation | Method of forming polycrystalline semiconductor thin film |
| US6815269B2 (en) * | 2002-05-08 | 2004-11-09 | Nec Lcd Technologies, Ltd. | Thin-film transistor and method for manufacturing the same |
| US7745822B2 (en) | 2003-06-27 | 2010-06-29 | Nec Corporation | Thin film transistor and thin film transistor substrate including a polycrystalline semiconductor thin film having a large heat capacity part and a small heat capacity part |
| US8017507B2 (en) | 2003-06-27 | 2011-09-13 | Nec Corporation | Method of manufacturing a polycrystalline semiconductor thin film |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2689596B2 (en) | 1997-12-10 |
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