JPH02283172A - Horizontal synchronizing separator circuit - Google Patents

Abstract

PURPOSE:To extract a horizontal synchronizing pulse not including an equalizing pulse by measuring the length of one horizontal period and masking a prescribed period of a composite synchronizing pulse based on the result of measurement. CONSTITUTION:A composite synchronizing pulse Pc is fed to a trailing detection circuit 41 and a pulse Pd for each trailing of the pulse Pc is extracted. When the pulse Pd is obtained, the count N represents the length of one horizontal period at preset and the value of a latch 23 represents the length of one horizontal period at one preceding horizontal period. A value L is inputted to comparator circuits 3138 via division circuits 24-26 and the count N is inputted to the comparator circuits directly. A pulse P1 from the circuit 31 is fed to a latch 34 as a clock and a pulse P2 from the circuit 32 is fed to a NAND circuit 35, and a pulse Pn is extracted for each horizontal synchronizing pulse Ph and fed to the latch 34. A pulse Pm is extracted from the latch circuit 34 and fed to an OR circuit 12 for masking and the horizontal synchronizing pulse Ph not including an equalizing pulse Pe is extracted from the circuit 12.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a horizontal synchronization separation circuit.

[Summary of the invention]

The present invention provides a synchronization separation circuit for horizontal synchronization pulses.
By measuring the length of one horizontal period and masking a predetermined period of the composite sync pulse based on this measurement result, horizontal sync pulses that do not include equalization pulses can be stably separated regardless of the horizontal frequency. This is what I did.

(Prior Art) CRT displays are widely used as output devices for personal computers, but the standards for video signals output from personal computers vary depending on the manufacturer and model. In particular, the horizontal frequency can vary by more than twice as much. Furthermore, while the video signals of general television broadcasts are of the interlaced format, the video signals of personal computers are often of the non-interlaced format.

Therefore, in a multi-scan CRT display, that is, a CRT display that can display an image by automatically following the horizontal frequency even if the horizontal frequency is different, when separating the horizontal sync pulse from the composite sync pulse, , it is necessary to separate the horizontal sync pulse so that it does not contain the equalization pulse.

For this reason, as a synchronization separation circuit for such horizontal synchronization pulses, a monostable multi-by-break is controlled by a voltage obtained by frequency discrimination (f/■ conversion) of the composite synchronization pulse, and its output is used to equalize the horizontal synchronization pulses. A circuit that masks pulses has been considered.

Literature: Particularly, the specification and drawings of Hirama 63-54392 This invention attempts to solve these problems.

[Means to solve the problem]

For this reason, in this invention, the length of the horizontal period is measured and a predetermined period of the composite synchronization pulse is masked based on the measurement result to extract the horizontal synchronization pulse that does not include the equalization pulse. This is what I did.

(Operation) Does not include an equalization pulse regardless of the horizontal frequency [Problem to be solved by the invention] However, the above-mentioned synchronous separation circuit can only support horizontal frequencies of about 15 kHz to 30 kHz; Even if an attempt is made to expand the range, for example, from 15 kHz to 90 kHz, problems will arise in terms of variations and temperature characteristics.

〔Example〕

In FIG. 1, a composite synchronizing pulse Pc is supplied through a terminal (11) to an OR circuit (12) for masking equalization pulses, and its OR output is taken out to a terminal (13).

In this case, the format of the pulse Pc varies as mentioned above, but here, as shown in Figure 2, it is assumed that the pulse Pc is of the NTSC system, ph is the horizontal synchronizing pulse, and Pv is the vertical synchronizing pulse. .

Pe is an equalization pulse and IH indicates one horizontal period. Further, as shown in A of the same figure, the time points of 1/4H and 3/4H in each horizontal period are indicated by O marks and X marks.

Further, the clock CLCK is supplied as a count input to, for example, a 12-bit counter (22) through the terminal (21), and the pulse Pc is supplied to the falling edge detection circuit (41) to generate a pulse as shown in FIG. Pc
A pulse Pd is taken out at each falling edge of
) is supplied to the clear human power CL of the counter (22).

In this case, the clock CLCK has a frequency sufficiently higher than the horizontal frequency of the pulse Pc, in this example, the pulse Pc.
The horizontal frequency at c is about 15kHz to 128k)
(Since the target is up to z, it is 16M) Iz. Further, the switch circuit (42) is used to ignore the pulse Pd when the equalization pulse Pe is generated, and is basically always on, although the details of its operation will be described later.

Therefore, the counter (22) is set to 1 by the pulse Pd.
It is cleared every horizontal period, and the clock CLC
As shown in the second diagram, the count value N is "0" when the pulse Pd occurs in each horizontal period.
” and then gradually increases in size. In addition, pulse Pd
When cleared by , the count value N indicates the length of one horizontal period of the pulse Pc.

Then, this count value N is supplied to the D input of the latch (23), and the pulse Pd is supplied to the D input of the latch (23).
4) is supplied as a clock to the latch (23). Note that the switch circuit (44) is the same as the switch circuit (44).
This is the same as 2).

Therefore, the latch (23) latches the count value N of the counter (22) every horizontal period with the pulse Pd, and the counter (22) also latches the count value N of the counter (22) with the pulse Pd.
When cleared by d, this clearing is done by the latch (23
) is delayed by the period of the pulse width of the pulse Pd, so the count value N of one horizontal period immediately before is latched in the latch (23).

That is, when a pulse Pd is obtained for each horizontal period, the count value N indicates the current (latest) length of one horizontal period, and the value of the latch (23) is equal to the length of the current (latest) one horizontal period. This indicates the length of the horizontal period.

This value is then supplied to the division circuits (24) to (26) and divided by the size of, for example, 1/4.3/4.6/4, respectively, and the quotient is the comparator circuit (31) to (26). 33), and the count value N is supplied to the B inputs of the comparison circuits (31) to (33).

Therefore, from the output terminal (A<B) of the comparator circuit (31), as shown in the second diagram, the signal is transmitted for a period of N > 1/4 L, that is, from the time point of 1/4H (time point marked with ○). During the period until the next pulse Pd, a pulse P1 of "H° level" is obtained, and from the output terminal (A<B) of the comparator circuit (32),
As shown in FIG. F, the period N=3/4H, that is,
During the period from the 3/4H time point (the time point marked with an x mark) to the next pulse Pd, a pulse P2 at the "H" level is obtained.

Then, the pulse P is supplied to the latch (34) as a clock input, and the D input of the latch (34) is set to the ``H'' level. Furthermore, the pulse PdP2 is supplied to the NAND circuit (35), and the pulse Pn becomes "L" level for each horizontal synchronizing pulse Ph as shown in FIG.
is taken out, and this pulse Pn is supplied to the clear manual power CL of the latch (34).

Therefore, as shown in FIG.
is taken out.

Then, this pulse Pm is supplied to the OR circuit (12), and from the OR circuit (12), as shown in FIG.
A falling pulse, that is, a horizontal synchronizing pulse Ph, is obtained every falling edge of .

Therefore, the horizontal synchronization pulse Ph that is separated from the composite synchronization pulse Pc and does not include the equalization pulse Pe is taken out to the terminal (13). Note that at this time, the pulse width of the extracted pulse Ph changes during the period of the vertical synchronization pulse Pν, but this may be made constant by monostable multi-by-break or the like as necessary.

In this case, the switch circuits (42), (44
) is controlled as follows.

That is, the comparison output P2.P, which becomes H'' level when N<3/4L and N<6/4L, is taken out from each output terminal (A<B) of the comparison circuits (32) and (33). ,
These outputs P, , P, are supplied to the logic circuit (51), and from the logic circuit (51), 3/4 L < N
<6/4 When L... α = ``'H'' level When other than the above, the signal α with α = ``'L'' level is extracted. Then, this signal α is supplied to the switch circuit (42) as its control signal, and is also supplied to the switch circuit (44) as its control signal through the OR circuit (52), and the switch circuit (42)
, (44) is turned on when α=゛H''.

Therefore, as shown in FIG. 3, at the time of 1/2H, that is, at the time of the equalization pulse Pe0, the state is α-"L", so the switch circuits (42) and (44,) are off, and the equalization pulse The pulse Pd detected from Pe is ignored, and as described above, the counter (22) and latch (23) are cleared and latched by the pulse Pd every one horizontal period.

Furthermore, the output terminals (A
=B), pulses Q, Q3, which are at "H" level when N=3/4L and N=6/4L, respectively, are taken out.
These pulses Q, ,Q, are supplied to the logic circuit (51), and from the logic circuit (51), (N≦3/4L or 6/4L≦N) is the maximum expected number of equalization pulses PeO. For example, when the signal β is 64 times in a row, β=゛HII level.Other than the above, β= II L. This signal β is output from the OR circuit (
52) to the switch circuit (44) as its control signal, and the switch circuit (44) receives β=“[■“”
It is turned on when

Therefore, the horizontal period I] has significantly increased (from 374
(less than or equal to 674) and this state continues for more than 64 horizontal periods, the horizontal period H after the change is latched in the latch (23), and from then on, the vertical synchronizing pulse Pu is taken out.

〔Effect of the invention〕

In this way, according to the present invention, regardless of the horizontal frequency, the length of the 1 horizontal period is measured, the time point of 1/4H of the 1 horizontal period is detected, and the next horizontal period is started from this 1/4H time point. The period up to the synchronization pulse Ph, the composite synchronization pulse P
Since the horizontal synchronizing pulse Ph is obtained by masking the horizontal synchronizing pulse c, it is possible to obtain a horizontal synchronizing pulse ph that does not include the equalizing pulse Pe over a wide range of horizontal frequencies, such as 15 kHz to 128 kl (z).

Moreover, as is clear from the above, there are no parts affected by temperature or the like, and therefore the operation is stable. Further, no adjustment is required.

Furthermore, the division circuit (24) only needs to shift the parallel data representing the value by two bits to the right and supply it to the comparison circuit (31), and is not actually required to be provided as hardware. Furthermore, the division circuit (25) only needs to add the parallel data of the value to the data shifted to the right by 2 bits and the data shifted to the right by 1 bit. , it is only necessary to add the data obtained by shifting this one bit to the right, so the cost is low.

[Brief explanation of drawings]

FIG. 1 is a system diagram of an example of the present invention, and FIGS. 2 and 3 are diagrams for explaining the same. (12), (23), (34) are latches, (2
2) is a counter, (24) to (26) are division circuits, (3
1) to (33) are comparison circuits, and (51) is a logic circuit.

Claims (1)

[Claims] A counter that measures the length of one horizontal period of a composite synchronization pulse, a latch that latches the count value of this counter at the horizontal period of the composite synchronization pulse, and a count output of the counter and the latch. A circuit that forms a first pulse at a time point between the horizontal sync pulse and the equalization pulse in the composite sync pulse, and a circuit that masks the composite sync pulse based on this first pulse. A horizontal synchronization separation circuit having a horizontal synchronization pulse which does not include the equalization pulse from the mask circuit.