JPH02284254A - Data transfer system for multiprocessor system - Google Patents

Abstract

PURPOSE:To reduce the queuing time of each processor for a global bus, and to improve the performance of whole system by providing each processor with a data transfer regulating means. CONSTITUTION:The processors 11, 21, 31 store write-in data and read-out data temporarily in storing means 13, 23, 33 installed separately through the global bus 5. Timers 12, 22, 32 to count the lapse of prescribed time from the genera tion of a reference signal are set at different time for every rocessor, and trans fer processing means 16, 26, 36 access the global bus differently from the proces sor after the lapse of the prescribed time of the timers, and transfer and process the data stored in the storing means through the global bus. Accordingly, each processor can access the global bus at timings different from each other, and since access processing to the global bus is executed by other transfer processing means, the processor can execute other processing during that time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer method for a multiprocessor system, and more particularly to a data transfer method for a multiprocessor system that transfers data via a global bus.

[Conventional technology]

Numerical control devices, robot control devices, and the like employ multiprocessor systems that use a plurality of processors to control a large number of axes at high speed.

The multiprocessor systems used in such control devices typically require several ms (approximately 8
There is a reference signal (ITP (interpolation) cycle signal) that is output every m5), and each processor performs data transfer processing every time this reference signal is output.

[Problem to be solved by the invention]

Therefore, after a certain period of time has elapsed since the reference signal was generated, each processor accesses the global bus at the same time. As a result, the frequency of use of the global bus per unit time is uneven, resulting in an increase in waiting time for accessing the global bus, resulting in a problem that the performance of the entire system is degraded.

The present invention has been made in view of the above points, and an object of the present invention is to provide a data transmission method for a multiprocessor system that reduces the waiting time of the global bus of each processor and improves the performance of the entire system. .

[Means to solve the problem]

In order to solve the above problems, the present invention provides a data transfer method for a multiprocessor system in which data is transferred between each processor in the multiprocessor system via a global bus. a storage means for temporarily storing read data; a timer having a different time set for each processor and elapses the elapsed time from generation of a reference signal; accessed separately from the processor,
Each of the processors is provided with data transfer adjustment means comprising a transfer processing means for transferring the write data and read data stored in the storage means via a global bus, and the global bus transfers the data between the processors. A data transfer method for a multiprocessor system is provided, which is characterized in that it is configured to be accessed at different timings.

[Effect]

The processor temporarily stores write data and read data in separately provided storage means via the global bus. A timer that measures the elapse of a predetermined time from the generation of the reference signal is set to a different time for each processor.

The transfer processing means accesses the global bus separately from the processor after a predetermined time of the timer has elapsed, and transfers the data stored in the storage means via the global bus. Therefore, each processor can access the global bus at different timings.

Further, since access processing to the global bus is performed by another transfer processing means, the processor can execute other processing during that time.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the overall configuration of a multiprocessor system that is an embodiment of the present invention.

Here, a multi-processor system will be explained using a several' direct control device as an example.

Processor modules 1.2 and 3 are connected to global bus 5. Since each processor module has the same configuration, only processor module 1 will be described.

Processor module 1 has a microprocessor 11 that controls the entire module. A ROM that stores a system program, a RAM that stores various data, etc. are connected to the microprocessor 11 via a local bus, but the description of these devices will be omitted in this embodiment.

Conventionally, the microprocessor 11 directly accessed the global bus 5 via the bus control circuit 15. In this embodiment, the microprocessor 11 is the data transfer adjustment circuit 1.
6 accesses the global bus 5. However, depending on the processing content of the microprocessor, it is also possible to directly access the global bus 5.

The data transfer adjustment circuit 16 includes a timer 12, a RAM 13, and a DMA controller 14. timer 12
is connected to an ITP generation circuit 4 which generates an ITP (interpolation) periodic signal 4a. The timer 12 measures the elapse of a predetermined time in synchronization with the input of the ITP (interpolation) periodic signal 4a,
The fact that a predetermined time has elapsed is output to the DMA controller 14.

The RAM 13 temporarily stores write data and read data of the microprocessor 11. When the DMA controller 14 receives the predetermined time elapsed output 12a from the timer 12, it transfers the write data and read data from the RAM 13 via the bus control circuit 15 and the global bus 5.

The bus control circuit 15 secures the right to use the global bus 5 and operates according to instructions from the microprocessor 11 or the DMA controller 14. That is, the bus control circuit 15 outputs a bus in-use signal when using the global bus 5, and a bus request signal when it wants to use the global bus 5, to the other bus control circuits 25 and 35, and outputs a bus request signal to other microprocessors.・Module is Global Bus 5
When using the bus busy signal, it outputs a bus busy signal to the microprocessor 11 or DMA controller 14.

Next, the operation of this embodiment will be explained. FIG. 2 is a diagram showing a time chart of the states that each processor module has on the global bus 5.

Each processor 11.21 and 31 stores in advance which area on the global bus 5 is to be read on the RAM 13.23 and 33, and at the same time the IT
The timer 12.2 determines how much time has passed since the P periodic signal 4a before accessing the global bus 5.
2 and 32. Approximately O for timer 12
ms, timer 23 is programmed with approximately 2 ms, and timer 32 is programmed with approximately 4 ms.

Therefore, at the time when the ITP periodic signal 4a is output, the processors 11, 21 and 31 transfer the write data to the RAM 13.
．． Write to 23 and 33. Since the timer 12 is Oms, it immediately secures the right to use the global bus 5 and executes data writing and reading processing via the global bus 5. This writing and reading is performed by the processor 11 using the RA.
The data written in M13 is transferred to the global bus 5, and the data written in the RAM 13 in the area to be read is read via the global bus 5, and the data is transferred to the RAM 23.
This is done by storing it in .

In this way, when all accesses of the processor module 1 to the global bus 5 are completed, D M
, A, the controller 14 outputs a transfer completion signal 14a to the processor 11. This transfer completion signal 14a
After receiving the data, the processor 11 reads the data from the RAML3.

The DMA controller 24 of the processor module 2 secures the right to use the global bus 5 after the time programmed in the timer 22, that is, 2 ms has elapsed since the ITP periodic signal 4a, and writes and reads data in the same manner as the processor module 1. Execute. Further, the DMA controller 34 of the processor module 3 secures the right to use the global bus 5 after 4 ms from the ITP cycle signal 4a, and executes writing and reading of data in the same manner as the processor module 1.

As described above, according to this embodiment, as is clear from FIG. 2, each processor module 1.2 and 3 can use the global bus 5 without access contention. Additionally, since accessing the global bus 5 generally takes longer than accessing it locally, the processors in each processor module do not need to access the global bus directly, which reduces the average external bus cycle of the processor and improves processor performance. can be improved.

In this embodiment, a case where the present invention is applied to a numerical control device has been described, but the present invention can be similarly applied to a robot control device.

Effects of the Invention As explained above, according to the present invention, there is an effect that the waiting time when the processor in each processor module uses the global bus can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of a numerical control device having a multiprocessor system, which is an embodiment of the present invention, and FIG. 2 is a time chart showing a state in which each processor module monopolizes the global bus. be. 1.2.3 11.21.31 12.22.32 13.23.33 14.24.34 15.25.35 Processor module ITP generation circuit Global bus Microprocessor timer AM DMA controller bus control circuit 6 ．． 26. Data transfer adjustment circuit patent applicant FANUC Co., Ltd. agent Patent attorney Takeshi Hattori

Claims (4)

[Claims] (1) In a data transfer method for a multiprocessor system in which data is transferred between each processor in the multiprocessor system via a global bus, the processor temporarily stores write data and read data via the global bus. storage means; a timer having a different time set for each processor and counting the elapsed time from generation of a reference signal; accessing the global bus separately from the processor after a predetermined time elapsed by the timer; Each of the processors is provided with data transfer adjustment means comprising a transfer processing means for transferring the write data and read data stored in the storage means via a global bus, and the global bus transfers the data between the processors. A data transfer method for a multiprocessor system characterized by being configured to be accessed at different timings. (2) The data transfer method for a multiprocessor system according to claim 1, wherein the multiprocessor system is a numerical control device or a robot control device. (3) A data transfer method for a multiprocessor system according to claim 1, wherein the transfer processing means is a DMA controller. (4) The data transfer method for a multiprocessor system according to claim 1, wherein the reference signal is an ITP (interpolation) periodic signal.