JPH02285461A - Multi-microprocessor equipment - Google Patents

Abstract

PURPOSE:To improve the mounting efficiency of a circuit element as the whole equipment by providing a transfer means for a microprogram between a microprocessor equipment of at least one group and a microprocessor equipment of the other group. CONSTITUTION:A microprocessor equipment of one group in microprocessor equipments of plural groups reads out a microprogram of the processing allocated to a microprocessor equipment of the other group from a main storage device 18. Subsequently, the microprogram is transferred to a storage means (local RAM 3b) of the target microprocessor equipment of the other group through transfer means (decoder 19, flip-flop 22, buffer 24, OR gate 25) provided newly and stored therein. Therefore, in the microprocessor equipment of the other group, a local ROM for reading out the microprogram from the main storage device 18 becomes unnecessary. In such a way, the number of circuit elements in the whole equipment decreases, and its mounting efficiency is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-microprocessor device comprising a plurality of sets of microprocessor devices.

C. Prior Art FIG. 2 is a block diagram showing a conventional configuration of this type of multi-microprocessor device. In the figure, 1 is a multi-microprocessor device, 2a and 2b are microprocessors, and 3a and 3b are random access memories (RA) that store microprograms and data for operating the corresponding microprocessors 2a and 2b, respectively.
M: Hereinafter referred to as local RAM>, 4a and 4b are read-only memories (ROM: hereinafter referred to as local ROM) that store microprograms necessary for processing at the beginning of startup, 5a and 5b are microprocessors 2a and 2b 7 is a buffer door for outputting the address information outputted by each to the address bus 6 which is a common bus for these microprocessors, and 7 is a central processing unit which is a host metering unit for the address information on the address bus 6! 17 is a buffer for outputting to the host address bus 8; Bidirectional buffers for transmitting and receiving data; 13a, 13b and 14a, 14b are bidirectional buffer doors for transmitting and receiving data between the data bus 12 and the microprocessors 2a, 2b; 15 is a microprocessor 2a; 2b is a commonly used shared memory; 16 is a reset signal input to each multiprocessor 2a, 2b when the central processing unit 17B system is started; 1;
8 is a main storage device that stores programs, data, etc. for processing executed by each microprocessor 2a, 2b.

Here, microprocessor 2a, local JL, RAM
3a, o-cal ROM 4a, buffer 15a1 buffer'
13a and 14a constitute a first set of microphone 0 processor devices. Further, the microprocessor 2b, local RAM 3b, local ROM 4b, buffer door 5b, buffers 13b and 14b constitute a second set of microb0 setter devices.

Next, the operation related to the above configuration will be explained.

First, the central processing @11f17 when starting the system,
Outputs a reset signal 16 and outputs a reset signal 16 to each microprocessor 2a.
, 2b. Then, each microprocessor 2a
, 2b is the input trigger for this reset signal 16,
After reading the initialization routine microprogram stored in advance in the local ROMs 4a and 4b and starting operation, and executing the initialization process including the self-diagnosis function,
Central office jl! The system waits for a startup command issued from the device 17.

Here, to explain the operation of the first set of microprocessor devices as a representative example, the microprocessor 2a is the central processor ni! ! When a start command is input from 17, the microprogram for the process assigned to it is stored in the main memory!
18, address information indicating the storage address of the microprogram is sent to the host address bus 8 via the buffer 5a→address bus 6→buffer 7 route.

Then, the microprogram stored at the address indicated by the address information is read from the main storage device 118. This microprogram is the host data bus 9
The data is inputted to the data input terminal (D) of the local RAM 3a via the route → buffer 11 → data bus 12 → buffer 14a, and written to the local RAM 3a by a write command from the microprocessor 2a.

In this way, the microprocessor 2a stores the microprogram for the process assigned to it in the local RAM 3a.
If the microprogram is stored in the local RAM 3a, the microprogram waits for a processing start command from the central processing unit 17, but when the processing start command is input, processing according to the microprogram stored in the local RAM 3a is started.

The above operations are performed in exactly the same manner for the second set of microprocessor devices.

[Problem to be solved by the invention]

The conventional multi-microprocessor device is configured as described above, and each microprocessor 2a, 2b executes the process assigned to it by the initialization routine microprogram stored in advance in the local ROM 4a, 4b at the time of startup. Individually read the microprograms from the main memory @18 and store them in the local RAM3a.
, 3b. Therefore, it is necessary to provide local ROMs 4a and 4b corresponding to the microprocessors 2a and 2b, respectively, and Im! There has been a problem in that the overall mounting efficiency of circuit elements is reduced.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a multi-microprocessor device that can improve the mounting efficiency of circuit elements in the entire device.

[Means for Solving the Problems] A multi-microprocessor device according to the present invention has a storage means (RAM 3a) for storing microprograms.
, 3b) and a microprocessor <2a that executes processing according to the microprogram stored in this storage means.
.
), and one set of microprocessor devices transfers the microprograms for processing assigned to the other set of microprocessor devices to the main memory F (18) of the host computer II machine. >, and is transferred to the storage means (local RAM 3b) of the target microprocessor device of another set via the transfer means and stored therein.

[Effect]

In this invention, one set of microprocessor apparatuses among a plurality of sets of microprocessor apparatuses reads a microprogram for a process assigned to another set of microprocessor apparatuses from the main storage device (18), and transfers it to a newly provided transfer unit. storage means (local RAM
3b) and store it.

Therefore, in the other sets of microprocessor devices, there is no need for a local ROM for reading the microprogram from the main memory (18). As a result, the number of circuit elements in the entire device is reduced, improving its packaging efficiency. In addition, by providing a transfer means, the microprocessor W1s of one set can read the microprogram stored in the storage means (〇-Cal RAM3b) of the other set of microprocessor devices, and analyze the cause of malfunction etc. It will also be possible to do so.

〔Example〕

Hereinafter, the present invention will be explained in detail based on examples.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 4, the same parts as in the conventional configuration in FIG. 2 are indicated by the same symbols.
The 〇-power ROM 4b installed on the side was deleted, and the decoder 19, flip-flop 22, and buffer 2
4. The OR gate 25 has been newly installed.

Decoder 19, flip-flop 22, buffer 24,
The OR gate 25 is connected to the first set of microprocessors 2a.
The decoder 19 constitutes a transfer means for transferring the microprogram from the microprocessor 2b side to the second set of microprocessor 2b side, and the decoder 19 decodes the address information output from the microprocessor 2a and generates the reset signal 20 or reset release signal. Outputs 21. Of these, the reset signal 20 is input to the OR gate 25 together with the reset signal 16 output from the central processing unit W117, and is input to the clock input terminal <C> of the flip-flop 2 via the OR gate 25. In addition, reset release signal 2
1 is input to the reset input terminal (R) of the flip-flop 22.

And the set output terminal (Q) of the flip-flop 22
The output signal is input as a reset signal 23 to the reset input terminal (R1) of the microprocessor 2b.
On the other hand, is the buffer 124 a bidirectional buffer along with the buffer 5b? It is connected in parallel to the buffer 5b so as to constitute.

Next, the operation related to the above configuration will be explained.

First, the microprocessor 2a of the first set stores the microprogram for the process assigned to it in the local RAM 3.
Since the operation of storing the microprogram in the microprocessor a is the same as the conventional one, its explanation will be omitted, and the operation of storing the microprogram in the 0-cal RAM 3b of the second set of microprocessors 2b will be explained.

When starting up the system, the central processing unit 17 outputs the reset signal 16 as in the past, but this reset signal 1
6 is input to the clock input terminal of the flip-flop 22 via the OR gate 25. As a result, the flip-flop 22 enters the set state, and its set output terminal (
A reset signal 23 is output from Q). This results in
Microprocessor 2b is reset and remains in its reset state until flip-flop 22 is reset. Therefore, the address information aSS and data information Nsl of the microprocessor 2b continue to be maintained in a high impedance state.

On the other hand, after receiving the reset signal 16, the microprocessor 2a of the first set executes the microprogram for the process assigned to it in the local RAM 3a as before.
After the processing is completed, the microprogram for the process assigned to the second set of microprocessors 2b is read out from the main storage device 18 and temporarily loaded into the local RAM 3a.

After this, import this imported microprogram into 0-calR
In order to transfer and store it in AM3b, address information indicating the storage address is transferred from buffer 5a → address bus 6 →
The microprogram for the second set of microprocessors 2b is supplied to the address input of the local RAM 3b via the buffer 24 route, and is also temporarily loaded into the local RAM 3a from the buffer 13a → data bus 12 →
The buffer 14b is supplied to the data input of the local RAM 3b, and the microprogram is transferred to the local RAM 3b.
Add 1 to b.

When the transfer of the microprogram for the second set of microprocessors 2b is completed in this way, the microprocessor 2a inputs address information for generating the reset release signal 21 to the decoder 19. A reset release signal 21 is outputted from. This reset release signal is input to the reset input terminal (F?) of the flip-flop 22, so the flip-flop 22 is reset. This allows its set output terminal (Q
) becomes inactive, the microprocessor 2b is released from the reset state, and starts processing according to the microprogram stored in the local RAM 3b.

On the other hand, when diagnosing the malfunction of the microprocessor 2b, the microprocessor 2a sends the address information for generating the reset signal 20 to the decoder 1.
9 and causes the decoder 19 to generate a reset signal 20. Then, the flip-flop 22 is set by this reset signal 20, and its set output terminal (Q
) outputs a reset signal 23. The microprocessor 2b is brought into a reset state by this reset signal 23. Therefore, the microprocessor 2a is 0-cal R
The microprogram in the local RAM 3b is read into the RAM 3a by a route in the opposite direction to that when the microprogram was transferred from the AM 3a to the AM 3b, and is analyzed to diagnose the cause of malfunction.

In this way, in this embodiment, since the microprogram transfer means is provided between the first set of microprocessors 2a and the second set of microprocessors 2b,
On the side of the second set of microprocessors 2b there is a local R
There is no need to provide an OM, and the mounting efficiency of circuit elements is improved. Further, even if the second set of microprocessors 2b malfunctions, the cause can be analyzed by reading the contents of the local RAM 3b into the first set of microprocessors 2a.

In the above embodiment, there are two sets of microprocessor devices, but the present invention can be similarly applied to a case where there are three or more sets of microprocessor devices. Furthermore, although the configuration is such that only one set of microprocessor devices can transfer the microprogram to another set of microprocessor devices, a similar transfer function may be added to all the sets.

〔Effect of the invention〕

As explained above, according to the present invention, a microprogram transfer means is provided between at least one set of microprocessor devices and another set of microprocessor devices, so that all the sets of microprocessor devices have a main memory. It is no longer necessary to provide a local ROM for reading microprograms from the device, and the efficiency of mounting circuit elements in the device as a whole can be improved. Another advantage is that other sets of microprograms can be read out to easily diagnose malfunctions and the like.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a multi-microprocessor device according to the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional multi-microprocessor. 1...Multi-microprocessor system [, 2a, 2b,
...Microprocessor, 3a, 3b...Local R
AM, 4a, 4b/o-cal ROM, 5a, 5b, 7.
10.11.13a, 13b, 14a. 14b, 24...buffer, 6...address bus,
8... Host address bus, 9... Host data bus, 12... Data bus, 15... Shared memory, 1
6.20.23...Reset signal, 17...Central processing unit, 18...Main storage device, 19...Decoder,
21...Reset release signal, 22...Flip 70
Tsubu, 25...or gate. Note that the same or corresponding parts in the figures are indicated by the same reference numerals. calligraphy (spontaneous)

Claims (1)

[Scope of Claims] A plurality of sets of microprocessor devices each consisting of a storage means for storing a microprogram and a microprocessor that executes processing according to the microprogram stored in the storage means, each set of microprocessor devices is a multi-microprocessor device that reads microprograms for processing assigned to it individually from the main memory of a host computer, stores them in the storage means, and then executes processing according to the stored microprograms, at least one Transfer means for transferring a microprogram between the storage means of one set of microprocessor devices and the storage means of another set of microprocessor devices is provided, and the one set of microprocessor devices is assigned to the other set of microprocessor devices. A multi-microprocessor characterized in that the microprogram for the processing performed is read from the main storage device of the host computer, and transferred to and stored in the storage device of another target microprocessor device via the transfer device. Device.