JPH02287647A - Storage device - Google Patents

Abstract

PURPOSE:To reduce the hardware quantity of a write data register and to reduce the cost by following it by providing plural pieces of OR gates, and using each write data resister in common between plural pieces of write data. CONSTITUTION:In the case the operation command is a block write command, a bank control circuit 2 generates a command at 1 clock period interval to write data registers 5a, 5b through timing generating circuits 3a - 3d, address registers 4a - 4d and OR gates 7, 8. The circuits 3a - 3d sent out operation start signals SRT delayed by 1 clock period each and write instruction signals WE delayed by 1 clock period from the signals SRT to the corresponding banks 1a - 1d. Also, plural pieces of write data transferred at 1 clock period interval onto a write data line D are held extending over a period of 2 clocks in the registers 5a, 5b, and written in the banks 1a - 1d by synchronizing with the signals SRT, WE. In such a way, the hardware quantity of the registers 5a, 5b can be reduced, therefore, the cost can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a storage device installed in a data processing device, and particularly to a storage device that sequentially writes block-transferred write data to a plurality of banks. This is related to storage devices.

(Prior Art) A storage device installed in a data processing device is composed of n banks, and each of the n data transferred in blocks is sequentially written to each bank. There is.

FIG. 3 is a block diagram illustrating the configuration of such a storage device in the case of four banks, 11a to li.
d is a bank, 12 is a bank control circuit, 138 to 13d are timing generation circuits, 14a to 14d are address registers, and 15a to 15d are write data registers.

The bank control circuit 12 decodes an operation command sent from another device such as a central processing unit via the operation command line C, and if it is a block write command, it decodes the operation command sent from another device such as a central processing unit, and if it is a block write command, it decodes the operation command sent from another device such as a central processing unit. ~14
d and each of the write data registers 15a to 15d, operation commands are sequentially issued at intervals of one clock period T. As shown in the timing chart of FIG.
The operation start signal SRT and the write instruction signal WE are sent out delayed by one clock period T. Write data WD (
Do, Di, D2. D3) are sequentially held in the write data registers 15a to 15d and are sequentially written to the corresponding banks lla to lid while being held for a period of 4 clock cycles 4T. Although not shown in the figure, the addresses transferred on the address signal 4iA at intervals of one clock period T are transferred to the corresponding address registers 143-1.
It is held for a period of 4T at the same timing as the operation start signal SRT corresponding to 4d, and the corresponding bank lla~
is supplied to the address terminal of the lid.

Each write data held in the write data registers 15a to 15d for a period of 4T is actually 2T from when the corresponding operation start signal SRT falls to low until the corresponding write command WE returns to high state. It only needs to be valid for a period of .

(Problems to be Solved by the Invention) In the conventional storage device explained in FIGS. 3 and 4,
Since a timing generation circuit, an address register, and a write data register are provided for each bank, the amount of hardware increases. For timing generation circuits and address registers, an increase in the amount of hardware is not a major problem because of high integration and relatively small address bit widths, but for write data registers with large bit widths, the increase in the number of banks and the data There is a problem in that as the bit width increases, the amount of hardware increases, resulting in higher costs.

(Means for Solving the Problems) In the storage device of the present invention, each write data register is shared among multiple pieces of write data, thereby reducing the amount of hardware for the write data register and the associated cost reduction. It is configured to realize cost reduction.

Hereinafter, the operation of the present invention will be explained in detail together with examples.

(Embodiment) FIG. 1 is a block diagram showing the configuration of a storage device according to an embodiment of the present invention.

This storage device includes four banks 1a to 1d, a bank control circuit 2, timing generation circuits 3a to 3d installed corresponding to the four banks, and an address register 4a.
~4d, and write data registers 5a each shared by two banks.

5b, an OR gate 7.8, and related input/output signal lines.

The bank control circuit 2 decodes an operation command sent from another device such as a central processing unit via an operation command line C. If the operation command is a block write command, the bank control circuit 2 sequentially issues commands to each of the timing generation circuits 33 to 3d, address registers 4a to 4d, and OR gates 5a and 5b at intervals of one clock period T. As shown in the timing chart of FIG. 2, the timing generation circuits 3a to 3d supply the corresponding banks la to 1d with an operation start signal SRT delayed by one clock cycle MT, and also supply an operation start signal SRT delayed by one clock cycle MT. A write instruction signal WE delayed by a clock period T is sent out. As shown in the timing chart of FIG. 2, the write data WD (DO, Dl, D2, D3) transferred on the data line at intervals of the clock cycle T are such that the first write data DO is transferred to the write data register 5a. is held for a period of 2T, and the next data D1 is stored in the write data register 5.
b for a period of 2T.

Also, the third data D2 is the write data register 5a.
The last data D3 is held in the write data register 5b for a period of 2T. The write data Do-D3 held in the write data registers 5a and 5b for a period of 2T is sequentially transferred to the banks in synchronization with the operation start signal SRT and write instruction signal WE sequentially supplied from the corresponding timing generation circuits 3a to 3d. 1a to 1d.

Although not shown in the figure, the addresses transferred onto the address signal line A at intervals of one clock cycle T are:
It is held in the corresponding address registers 4a to 4d for a period of 4T at the same timing as the corresponding operation start signal SRT, and is supplied to the address terminals of the corresponding banks 1a to 1d.

In this way, when writing a block of data, one write data register 5a is shared between bank la and the IC, and the other write data register 5b
is shared between banks 1b and 1d.

In the case of block reading, the operation is similar to the block writing described above except that the timing generation circuit does not generate the write instruction signal WE. Also, each bank l a-m
The read data read from ld is sequentially selected by the selector 6 under the control of the bank control circuit 2, and outputted onto the read data line 0 as four consecutive read data.

(Effects of the Invention) As described above in detail, the storage device of the present invention has a configuration in which the write data register is shared among multiple pieces of write data, so the amount of hardware for the write data register is reduced. This will result in lower costs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a storage device according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, and FIG. 3 shows the configuration of a conventional storage device. The block diagram and FIG. 4 are timing charts for explaining the operation of FIG. 3. 1a to 1b--Bank, 2-Bank control circuit, 3
a to 3d...timing generation circuit, 4a to 4d...
Address register, 5a...Write data register shared by banks 0 and 2, 5b...Write data register shared by banks 1 and 3, 6...Selector, C...operation command signal Line, A...Address line, D...
...Write data line, O...Read data line.

Claims (1)

[Scope of Claims] Each of n pieces of write data (n is an integer) that are continuously transferred is held in a plurality of write data registers for a time longer than the transfer interval, and sequentially written to n banks. 1. A storage device in which each write data register is shared among a plurality of pieces of write data.