JPH02287656A - Communication controller - Google Patents

Abstract

PURPOSE:To effectively eliminate an obstruction to the processing efficiency of a CPU part and the processing of a host by providing a means for fetching the receiving data from a receiving FIFO queue without executing a write operation to an external memory on a memory access control part. CONSTITUTION:An address/control signal generating part 8 in a memory access control part 4 reads out receiving data 104 by a control signal 103 inputted from a receiving FIFO gueue 3 in accordance with a command inputted through an internal data bus 101 from a CPU part. Subsequently, the read-out data is sent to an external memory through a buffer 13 and written therein. In this case, write is controlled by a bus request signal BUSRQ, a bus acknowledge signal BUSAK and a memory write signal MWR. In this state, in the case it is not a frame addressed to the own station, the receiving data is fetched from the queue 3 without writing it in the external memory through the signals BUSRQ, BUSAK and MWR and a register 14, etc., and an obstruction to the processing efficiency of the CPU part and the processing of a host can be eliminated effectively.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a communication control device.

[Conventional technology]

Conventionally, as shown in FIG. 3, a communication control device consists of a receiving section 2, a receiving FIFO queue 3, a memory access control section 4, and a CPU section 1 for controlling each of these sections. It is configured. Furthermore, as shown in FIG. 4, a communication system including such a communication control device includes a host 6 and a memory 7 connected to the communication control device 5 by a system bus 102. 7 is generally shared by the communication control device W5 and the host 6. The memory 7 is used to store received frames, and when a frame is received by the communication control device 5, this frame is written into the memory 6, and when this frame reception is notified to the host 6,
The host 6 interprets the data within the frame and performs necessary processing.

Furthermore, in general, communication systems use frames in the format shown in Figure 5, in which the source address represents the transmitting station, and the destination address represents the destination station. It represents. Further, the time/slot/sort of the control information includes information indicating what type of frame the frame is. For example, the frame may include data to be processed by the communication control device 5 itself, or
It contains information that it is simply a frame containing data from one station's host to another station's host. By reading this information, the receiving side determines whether the frame is addressed to itself and what type of frame it is.

-m, frame reception in the communication control device is performed as follows.

3 and 11, the CPUI is the host 6
When receiving an instruction to start receiving from the receiver, the receiver 2 is activated to start receiving. After receiving the signal on the communication medium and confirming the beginning of the frame, the receiving unit 2 converts the frame data into a fixed bit length (for example, 8 bits).
- length) and input them to the reception FIFO queue 3. This operation is the same as the normal reception clock! This will be done in one step.

When the data input to the reception FIFO queue 3 is waiting for output, the CPU detects this state and transfers the data to the reception FIFO queue 3.
The address part and control information part of the received frame are extracted from the IFO queue 3, and it is checked whether the frame is addressed to the local station and what kind of frame it is. If the frame is addressed to the own station and must be stored in an external memory, the memory access control unit 4 stores the received frame in an area of the external memory prepared in advance.
Activation is activated to write the remaining part of the frame input to IFO queue 3. Furthermore, if the frame is addressed to another station, that frame must be discarded. In this case, the method of discarding is to discard the receive FIFO
There is a method of resetting the queue 3, but with this method, if frames to be received next are continuously input to the reception FiFO queue 3, there is a risk that that data will also be lost. Also, in order to prevent this kind of situation, the structure of the receive FIFO queue 3 must be made more complex. Therefore, in order to ensure that only the target frame is deleted, the remaining frames must be stored in CPIJI itself. All the data is taken out from the reception FIFOq knee 3 or written to the external memory 7 using the memory access control unit 4, and for the hosts I to 6,
Otherwise, it is necessary to respond as if the message had not been received and proceed with the process without notifying the user that the message has been received.

[Problem to be solved by the invention]

In the conventional communication control device described above, a received frame is taken out from the reception FIFO queue 3, and if the frame is not addressed to the local station, the frame must be discarded. In the conventional communication control device described above, for this purpose, the remaining data is taken out from the reception FIFO queue 3 using the CPJ section 1 in the communication control device, or the remaining data is stored in the external memory 7 by the memory access control section 4. Processing must be done by writing.

This has the disadvantage that when processing is performed by the 020 unit 1, the 020 unit 1 is occupied with collecting data from the reception FTFO queue 3 and cannot respond to instructions from the host 6. Yes, also 020
When writing to the external memory 7 by the memory access control unit 4, the system bus 10 to which the host 6 and the communication control device 5 are connected so that the unit 1 is not occupied.
2 will be occupied, and even in this case, there is a drawback that processing in the host 6 may be disturbed.

[Means to solve the problem]

The communication control device of the present invention includes: a receiving unit that divides a digital signal received from a communication medium into data of a constant bint length and outputs the data; a receiving FIFO queue that inputs the received data output from the receiving unit; A communication control device including a memory access control unit that extracts received data from a FIFO queue and writes it externally, and a CPU unit that controls each unit such as the reception unit, reception FIFO queue, memory access, v1gi unit, etc. The control unit is configured to include means for extracting received data from the receive FIFO queue without writing to an external memory.

〔Example〕

Next, the present invention will be explained with reference to the drawings. The block diagram of the communication control device of the present invention is basically the same as the communication control device shown in FIG. 3 described above. The feature of the present invention lies in the functional means including the memory access control unit 4 in FIG. 3 and an interface with its surroundings. Therefore, in FIG. A partial block diagram is shown. The first embodiment will be described below with reference to FIGS. 1, 3, and 4.

As shown in FIG. 1, the memory access control unit 4 of this embodiment uses a reception FIFO also included in the communication control unit.
Corresponding to queue 3, address/control signal generation section 8, A
ND circuits 9, 10. The circuit includes an OR circuit 11, an inverter 12, a buffer 13, and a register 14.

In FIG. 1, when the address/control signal generator 8 receives a command sent from the 020 unit 1 (see FIG. 3) via the internal bus 101, the address/control signal generator 8 receives the command from the receive FIFO queue 3. The received data 104 is read in response to the control signal 103. The read received signal 104 is sent to the external memory 7 (see FIG. 4) via the buffer 13 and written therein. Regarding the write destination for the memory 7, the first address is given in advance by the 020 section 1, and each time data is written to the memory 7, the write address is incremented by one.

Furthermore, writing to the memory 7 is controlled by a bus request signal BUSRQ, a bus acknowledge signal BUSAK, and a memory write signal MWR.

In this way, the address/control signal generation unit 8
The received data 104 is sequentially written into the external memory 7. Each control signal for BUSRQ and BUSA is a signal that becomes active when it is 1. Therefore,
In FIG. 4, if BUSRQ is 1, the communication control device is connected to the system bus 102 (see FIG. 4).
When the response signal BUSAK to this request becomes 1, it means that the system bus 102 has been acquired by the communication control device.

The register 14 is a mode register for setting the operation mode of the memory access control unit 4.

The information held here consists of 1 bit, and this information is written by 020 part 1.

The 1-bit information output from the register 14 is A
ND circuit 9, inverter 12 and OR circuit 11, AN
The signal is sent to the D circuit 1, buffer 13, etc., and controls the input/output of data, control signals, etc. between the memory access control section 4 and the outside.

When the 1-bit information is set to 1, the output of the information causes the corresponding bus request signal B to be sent to the address/control signal generation section 8 in the memory access control section 4.
When each control signal such as USRQ, pass acknowledge signal BUSAK, and memory write signal 14%IR, and each data and address signal is valid, and the 1-bit information is set to 0, the above Each control signal and each signal are all invalidated. Therefore, even if the 020 unit 1 instructs the memory access control unit 4 to write the received data to the memory 7 when the 1-bit information is 0, the bus request signal is actually sent to the outside. BυSRQ is not in an active state, and on the other hand, the pass acknowledge signal BυSAK appears to be in an active state to the address-control signal generation unit 8. As a result, the address/control signal generator 8
In this case, it is determined that the system bus 102 has been acquired, and the received data is written one after another, but since the 1-bit information output from the register 14 is set to 0, the actual , the received data is not output on system bus 102 . Therefore,
These received data are retrieved from the receive FIFO queue 3 without being written to the external memory 7. As a result, if it is confirmed that the received frame is an unnecessary frame as judged from the control information and address information of the received frame, 1- when discarding the frame, This can be done without affecting the system bus 102 in any way.

Next, a second example will be described.

As already mentioned above, the block diagram of the communication control device of the present invention is basically the same as the communication control device shown in FIG. The feature of the present invention lies in the functional means including the memory access control section 4 in FIG. 3 and an interface with its surroundings. Therefore, in FIG. A partial block diagram centered on section 4 is shown. Below, Figure 2,
The second embodiment will be described with reference to FIGS. 3 and 4.

As shown in FIG.
Corresponding to the O queue 3, an address/control signal generation section 15
, a FIFO read signal raw signal generation furnace 16, a star 17, and an OR circuit 18.

In FIG. 2, when the memory access control unit 4 reads the received data 105 from the receive FIFO queue 3, it is first checked whether the ready signal 107 output from the receive FIFO queue 3 is active. This ready signal 107 is sent to the reception FIFO queue 3.
When this signal is active, the data read out from the receive FIFO queue 3 is valid. Therefore, in the memory access control unit 4, the ready signal 107
When it is confirmed that the
The received data 105 is sent to the IFO queue 3, and one piece of received data 105 is read out from the receive FIFO queue 3. By repeating this series of operations, the received data 105 is sequentially read out from the receive FIFO queue 3.

End signal 1 output from receive FIFO queue 3
08 is a signal indicating that it is the last data of the received frame. In the memory access control unit 4, when this end signal 10g becomes active,
The operation is stopped after reading the received data 105 and writing to the external memory 7 for that time.

In the address/control signal generation section 15, 020 section 1
In response to a command sent via the internal data bus 101, the received data 105 is read from the receive FtFO queue 3 and written to the external memory 7 using the method described above. In this case, the writing destination is
As in the case of the first embodiment described above, the first address is given in advance by the 020 unit 1, and each time data is written, one write address is added. In this way, the address/control signal generator 1
5, the received data 105 is sequentially written to the external memory 7.

F['O Read signal generation section 16, as in the case of address/control signal generation section 15, receives ready signal 107 and end signal 1 output from reception FIFO queue 3.
08 is input, and a read signal 106 is outputted via the OR circuit 18. The read signal output from the FIFO read signal raw signal generator 16 is the read signal output from the address/control signal generator 15 and the OF? It is ORed in the circuit 18 and sent as a read signal 106 to the reception FIF.
It is sent to O queue 3. Through these signals, F
The IFO read signal raw signal generation furnace 16 also receives the received data 10 from the receive FIFO queue 3 according to the command from the 020 unit 1.
5 can be taken out.

In this case, the difference from the address/control signal generation section 15 is that the extracted data is not used anywhere. The end of the data extraction operation is signaled by the end signal 10.
8.

In this embodiment, when the address/control signal generator 15 is activated to retrieve received data from the receive FIFO queue 3, the FIFO read signal raw signal generator 16 is simultaneously activated to retrieve received data. shall be applied. The register 17 is a mode register for setting the operation mode of the memory access control unit 4, as in the first embodiment described above. This register 17
The information held in the memory is composed of 1 bit, and is written by the CPU section 1. The written information is output as is to the address/control signal generation unit 15 and the FIFO read signal raw signal generation unit 16.

When 1 is set in register 17, that is, when 1 is output from register 17, the address
The control signal generating section 15 is in an enabled state and normal operation is performed. However, one FIFO read signal raw signal generation furnace 16 is in the disabled state, and the CPU section 1
It does not respond to instructions from the robot and remains stopped.

Conversely, when the register 17 is set to 0, the address/control signal generation section 15 is disabled, does not respond to instructions from the CPU section 1, and remains stopped. Retained.

On the other hand, the FIFO read signal raw signal generation unit 16 enters the blue state, and the CP instead of the address/control signal generation unit 15
In response to an instruction from the U section 1, the received data 105 is extracted. Therefore, in this state, the CPU section 1
When the memory access control unit 4 is instructed to write the received data to the external memory 7, the address/control signal generation unit 15 (in order to start the FIFO read signal raw signal generation unit 16) In reality, no access is made to the outside, and within the communication control device, the received data 105 is sequentially taken out from the receive FIFO queue 3, that is, as in the first embodiment. As in the case of FIG.

Note that in the case of this second embodiment, there is no need to set an address for the memory access control unit 4, and the reception FIFO queue 3 is stored until the end of the frame of the reception data 105.
Control is simplified since it is only necessary to read the information from . Also,
Just because the received frame is not needed, the received F
Since the IFO queue 3 and the receiving unit 2 are not reset and discarded, it is easy to receive and process another frame consecutively after this frame.

〔Effect of the invention〕

As described above in detail, the present invention is applied to a communication control device including a reception section, a reception FIFO queue, a memory access control section, and a CPU section, and is applied to a communication control device configured to include a reception section, a reception FIFO queue, a memory access control section, and a CPU section. By also providing f1 with the function of taking out the received data of from the reception FIFO queue without writing it to the external memory,
To effectively eliminate the problem of inhibiting the processing efficiency of the CPU section and the problem of occupying the system bus and interfering with host processing even when the received frame is not addressed to the own station. It has the effect of being able to

[Brief explanation of drawings]

FIG. 1 is a partial block diagram of a first embodiment of the present invention, FIG. 2 is a partial block diagram of a second embodiment of the present invention, and FIG.
Figure 4 is a system block diagram of a communication control device, Figure 4 is a block diagram of a communication system including the communication control device, and Figure 5
The figure is a diagram showing the format of a communication frame. In the figure, ■...CPU section, 2...
Receiving unit, 3... Reception FIFO queue, 4...
...Memory access control rn unit, 5...Communication control device, 6...Host, 7...Memory, 8, 15...Address/control Signal generation section, 9
．． 10...AND circuit, 11.18...
・OR circuit, 12... Inverter, 13...
-Buffer, 14.17...-Register, 16
・・・・・・FIFO read signal raw signal generation layer person Susumu Hara, patent attorney

Claims (1)

[Scope of Claims] A receiving unit that divides a digital signal received from a communication medium into data of a constant bit length and outputs the data; a receiving FIFO queue that inputs the received data output from the receiving unit;
A communication control device comprising: a memory access control unit that extracts received data from the reception FIFO queue and writes it to the outside; and a CPU unit that controls each unit such as the reception unit, the reception FIFO queue, and the memory access control unit; A communication control device characterized in that the access control section includes means for extracting received data from the reception FIFO queue without writing to an external memory.