JPH02288263A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To enhance the density of memory cells by providing two grooves on an insulating layer between a pair of transistor regions formed in a semiconductor layer through a predetermined interval. CONSTITUTION:In a semiconductor memory, a field effect transistor is composed of a depletion layer 22a in a semiconductor layer 22, a gate insulating film 26, a diffused source layer 23, and a diffused drain layer 24 and a gate electrode 25. A capacitor is composed of a first electrode 28 formed to cover the inner face of a trench groove 27 formed in the vicinity through a predetermined interval in an insulating layer 21 between two transistor forming regions, a dielectric layer 29 formed to cover the surface of the electrode 28, and a second electrode 30 formed in a recess along the groove 27 surrounding the layer 29. The electrode 28 is connected to the layer 23, and a bit line 35 is connected to the layer 24 through a contact hole 36 of an insulating film 34. As a result, even if an isolating width between the capacitors can be largely reduced, an isolation of insulators can be effectively performed, thereby realizing high density of memory cells.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device including a plurality of pairs of memory cells each consisting of a transistor and a capacitor.

[Conventional technology]

A conventional semiconductor memory device of this type (referred to as a dynamic RAM) will be explained with reference to FIG.

The figure shows two pairs of memory cells.

In the figure, l is a semiconductor substrate such as p-type silicon, 2.3 is a high concentration n-type source diffusion layer and drain diffusion layer which are diffused and spaced apart from each other inside the semiconductor substrate 1, and 4 is a source diffusion layer. p on the region between layer 2 and drain diffusion layer 3
Gate insulating film 5 such as type impurity-doped silicon oxide film
The gate electrode is made of p-type impurity-doped polysilicon layered through layers, and these constitute a field effect transistor.

In the region between two adjacent field effect transistors, a field oxide film 6 formed by selective oxidation technology is provided in the center, and each source diffusion layer 2 is formed on both sides of this field oxide film 6. Trench grooves 7 are formed on the sides. A heavily doped p-type channel cut layer IA is diffused under the field oxide film 6, and a dielectric layer 8 made of a thin oxide film connected to the field oxide film 6 is deposited on the inner surface of the trench groove 7. In addition, an electrode layer 9 made of polysilicon or the like is embedded in the recess formed by the dielectric layer 8. This dielectric layer 8, electrode layer 9 and trench groove 7
A capacitor is formed with the peripheral semiconductor substrate l.

Further, on the upper surface of the field oxide film 6, cell layers 1 and 10 made of polysilicon etc. are formed to be connected to the 111i electrode layer 9, and on the upper surface of the electrode layer 9, the groove width of the trench groove 7 is formed. A transfer gate 11, which also serves as a word line and has approximately the same size as , is formed via a cell plate insulator 11Ax2. Note that 13 is an insulating film that covers two pairs of memory cell formation regions, 14 is a bit line formed on the insulating film 13, and the bit line 14 is connected to the drain diffusion layer 3 through a contact hole 15 in the insulating film 13. It is connected to the.

Two pairs of memory cells having such a structure are formed on a plurality of semiconductor substrates 1 to constitute a semiconductor memory device with a predetermined capacity.

In this way, conventionally, the capacitors of a pair of memory cells are formed adjacent to each other inside the semiconductor substrate 1, and the field oxide film 6 is provided between both capacitors to separate them. It has a structure.

The writing and erasing operations in a semiconductor memory device having such a configuration are well known in the art, so a description thereof will be omitted.

[Problem to be solved by the invention]

By the way, in the conventional semiconductor memory device described above, since each capacitor of a pair of memory cells is formed adjacently inside the semiconductor substrate 1, the interaction between adjacent capacitors accumulated in each case is reduced. It tends to grow inside the semiconductor substrate 1. In order to ensure the insulation separation between the adjacent capacitors in such a (14 structure), the thickness of the field oxide film 6 is increased so that even when voltage is applied to the cell layers 1 and 10, the surface of the channel cut JIIA is Therefore, the bird's beak of field oxide film 6 expands in the substrate width direction, and the dimension of field oxide film 6 in the substrate width direction increases.

The need to ensure a sufficiently large width for the insulating layer between capacitors is an obstacle to increasing the density of memory cells, and the realization of large-capacity memories, which is increasingly desired in recent years. has become completely impossible.

The present invention was devised in view of these circumstances, and aims to increase the density of memory cells by ensuring insulation separation while shortening the separation width between each capacitor of a pair of memory cells. The purpose is to

[Means to solve the problem]

In order to achieve the above object, the present invention provides a semiconductor jfJ device including a plurality of pairs of memory cells each consisting of a transistor and a capacitor, and has the following configuration.

The semiconductor memory device of the present invention has an insulating layer and a semiconductor layer stacked on a semiconductor substrate, and has two transistors arranged at a predetermined distance in the insulating layer between a pair of transistor regions formed in the semiconductor layer. It is characterized in that a groove is provided and a capacitor is formed within this groove.

[Effect]

According to the FF4 configuration described above, since a capacitor is formed inside an insulating layer and an insulating layer is interposed between each capacitor of a pair of memory cells, the insulation isolation can be improved even if the separation width between the capacitors is shortened. becomes.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail based on the drawings.6 An embodiment of the present invention is shown in FIGS. 1 and 2.

The figure shows two pairs of memory cells.

In the figure, 20 is a semiconductor substrate made of p-type silicon, etc.;
1 is an insulating layer such as a silicon oxide film laminated on the entire surface of the semiconductor substrate 20, 22 is a semiconductor layer such as silicon doped with p-type impurities and is laminated on the surface of the insulating layer 21, and 23 and 24 are semiconductors. A high 7-degree n-type source diffusion layer 2 is formed by diffusion and spaced apart in the layer 22. A drain diffusion layer 25 is silicon oxidized on the surface of the region between the source diffusion layer 23 and the drain diffusion layer 24. This is a gate electrode made of polysilicon or the like that is laminated with a gate insulating film 26 made of a film or the like interposed therebetween. The depletion layer 22a of this semiconductor layer 22, the gate insulating film 26. Source diffusion layer 23. The drain diffusion layer 24 and the gate electrode 25 constitute a field effect transistor.

Further, 27 is an insulating layer 2 between two transistor formation regions.
Trench grooves are carved adjacent to each other at a predetermined interval inside the trench groove 27; 28 is a first electrode made of phosphorus-doped polysilicon formed on the inner surface of the trench groove 27; 29 is a first electrode of the first electrode 28; A dielectric layer 30 is made of a silicon oxide film or a nitride film deposited on the surface, and 30 is made of phosphorus-doped polysilicon or the like filled in a recess shaped along the trench groove 27 surrounded by the dielectric layer 29. These first electrodes 28. The dielectric layer 29 and the second electrode 30 constitute a capacitor. This first electric scraper 28 is connected to the source diffusion layer 23.

In addition, 31 is a cell plate formed continuously with the adjacent second electrode 30, 30, 32 is a transfer gate laminated on the surface of the second electrode 30 with a cell plate insulating film 33 interposed therebetween, and 34 is a pair of two The insulating film 35 covering the memory cell formation region is a focus line formed on the insulating film 34, and the focus line 35 is connected to the drain diffusion layer 24 through a contact hole 36 in the insulating film 34.

In this way, each capacitor of a pair of memory cells is formed inside the insulating layer 21, and an insulating layer 22 is formed between both capacitors.
1 is interposed between the capacitors, even if the separation width between the capacitors is extremely short, both capacitors can be reliably insulated by the insulating layer 21.

Incidentally, the isolation width between capacitors can be significantly shortened to at least 1/2 or less of the isolation width by a conventional field oxide film.

Further, as described above, the source diffusion layer 23 of the field effect transistor. If the drain diffusion layer 24 is formed in the semiconductor layer 22 made of a silicon film doped with p-type impurities, the short channel effect can be suppressed even if the distance between the source and drain is shortened. The area in the width direction can also be reduced.

Incidentally, since the write operation and erase operation in the semiconductor memory device of this embodiment are basically the same as those in the conventional device, their explanation will be omitted.

Next, an example of a method for manufacturing a semiconductor memory device having the above structure will be described with reference to FIG.

(2) A relatively thick insulating layer 21 such as a silicon oxide film is grown or deposited on the entire surface of the semiconductor substrate 20 by thermal oxidation. Or this insulation Ji2 in advance
1 is formed on a semiconductor substrate 20, for example, an SOI substrate (Si
licon on In5ulator). A semiconductor layer 22 made of a relatively thin silicon film doped with n-type impurities on the surface of this insulating layer 21 using CVD technology.
fully formed. A resist A is deposited on the surface of the semiconductor layer 22 except for the area where the trench groove 27 is to be formed, and using the resist A as a mask, the semiconductor layer 22 and the insulating layer 21 are etched to a predetermined depth using a reactive ion etching technique or the like. and obtain trench 427 [
See Figure 2 fat].

(2) After removing resist A, an impurity layer B such as arsenic is ion-implanted into a part of the semiconductor layer 22 and annealed to form an impurity layer B in the semiconductor layer 22. After this, C
A polysilicon film C doped with an n-type impurity such as phosphorus is formed over the entire surface by VD technology [see FIG. 2 (bl)].

(2) The polysilicon IIIC is removed by photoetching except for the inner surface of the trench groove 27 and the upper part of the impurity layer B to obtain the first electrode 28. After this, a thin silicon oxide film is formed on the entire surface using a thermal oxidation method, etc., and a polysilicon film E doped with n-type impurities such as phosphorus is formed on the entire surface using CVD technology [see tel in Figure 2]. ].

- Polysilicon film E and silicon oxide 11iD are removed by photoetching except for the upper part of first electrode 28 to obtain dielectric layer 29 and second electrode 30.
Figure (see d+).

(2) A silicon oxide film F is formed over the entire surface by a thermal oxidation method, and a polysilicon film G doped with an n-type impurity such as phosphorus is formed over the entire surface using a CVD technique (see tel in FIG. 2). This silicon oxide film F
! IIl 26 becomes the cell plate insulating film 33.

(2) The gate electrode 25 and the transfer gate 32 are obtained by patterning the polysilicon film G using a photoetching technique. Use these as masks
Type impurities are ion-implanted into the semiconductor layer 22 [see FIG. 2 (fl)].

(2) By annealing, the implanted ions are diffused into the semiconductor layer 22, and a source diffusion Jii 23 and a drain diffusion layer 24 are obtained (see FIG. 2Fg).

Note that the source diffusion layer 23 includes the impurity layer B described above.

(2) Thereafter, when the insulating layer 34 and the bit VA 35 are formed, the structure shown in FIG. 1 is obtained.

In the above embodiment, the trench for forming the capacitor is the trench groove 26, but this groove may be formed in an annular shape surrounding the transistor formation region, and the capacitor is formed in a part of this annular groove. It is also possible to implement it as follows.

〔Effect of the invention〕

As described above, in the present invention, each capacitor in a pair of memory cells is formed adjacent to each other inside an insulating layer,
Since this insulating layer is interposed between each capacitor, the isolation between the capacitors can be ensured even if the isolation width between the capacitors is significantly reduced compared to the conventional structure.

Therefore, it becomes possible to realize a high density of memory cells, and as a result, a large capacity memory can be manufactured.

[Brief explanation of drawings]

1 and 2 illustrate one embodiment of the present invention;
The figure is a longitudinal cross-sectional view of a semiconductor memory device, Fig. 2+a+ to Ig)
2 is a process diagram showing the manufacturing process of the semiconductor memory device of FIG. 1. FIG. FIG. 3 is a longitudinal sectional view showing a conventional semiconductor memory device. 20... Semiconductor substrate, 21... Insulating layer, 22... Semiconductor layer, 23... Source diffusion layer, 24... Drain diffusion layer, 25... Gate electrode, 26... - Gate insulating film, 27... Trench groove, 28... First electrode, 29... Dielectric layer, 30... Second electrode. Figure 1

Claims (1)

[Claims] (1) A semiconductor memory device comprising a plurality of pairs of memory cells each consisting of a transistor and a capacitor, which has an insulating layer and a semiconductor layer laminated on a semiconductor substrate; A semiconductor memory device characterized in that two grooves are provided at a predetermined interval in the insulating layer between a pair of transistor regions formed in the layer, and a capacitor is formed in the grooves.