JPH0228832B2 - DENKIRYOKENSHUTSUSOCHI - Google Patents
DENKIRYOKENSHUTSUSOCHIInfo
- Publication number
- JPH0228832B2 JPH0228832B2 JP7880381A JP7880381A JPH0228832B2 JP H0228832 B2 JPH0228832 B2 JP H0228832B2 JP 7880381 A JP7880381 A JP 7880381A JP 7880381 A JP7880381 A JP 7880381A JP H0228832 B2 JPH0228832 B2 JP H0228832B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- timer
- output
- circuit
- period
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
- G01R19/16576—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing DC or AC voltage with one threshold
- G01R19/1658—AC voltage or recurrent signals
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Measurement Of Current Or Voltage (AREA)
Description
【発明の詳細な説明】
この発明は、入力された電気量、例えばレベル
信号が所定値以上か否かを検出する検出装置に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a detection device that detects whether an input quantity of electricity, such as a level signal, is greater than or equal to a predetermined value.
従来、この種の装置として第１図に示すものが
あつた。第１図において、１は50Hzの交流源から
検出された信号Viが入力され、全波整流をする整
流回路、２は整流回路１の整流出力よりなる信号
V1が入力され、電圧VL1でレベル検出をする検出
回路、３は検出回路２の検出出力からなる信号
V2が入力され、動作時限０及び復帰時限T1（例え
ば５ｍｓ）を有するタイマ、４はタイマ３の信号
V3を入力し、動作時限０及び復帰時限T2（例えば
20ｍｓ）を有するタイマで、信号V0を最終的な
検出出力としている。 Conventionally, there has been a device of this type as shown in FIG. In Figure 1, 1 is a rectifier circuit that receives a signal V i detected from a 50Hz AC source and performs full-wave rectification, and 2 is a signal consisting of the rectified output of rectifier circuit 1.
A detection circuit receives V 1 and detects the level using voltage V L1 , and 3 is a signal consisting of the detection output of detection circuit 2.
V 2 is input, a timer with an operating time limit of 0 and a return time limit of T 1 (for example, 5 ms), 4 is the signal of timer 3.
Input V 3 , operation time 0 and return time T 2 (e.g.
20ms), and uses the signal V 0 as the final detection output.
次に第２図に示す波形図を参照して動作を説明
する。第２図の左側に示す期間イにおいて、信号
Viは電圧VNを超えないので、整流回路１の信号
V1が検出レベルVL1を超える期間t11は、時間T1
に達しない。従つて、タイマ３は信号V3を出力
せず、タイマ４も信号V0を出力しない。 Next, the operation will be explained with reference to the waveform diagram shown in FIG. In period A shown on the left side of Figure 2, the signal
Since V i does not exceed the voltage V N , the signal of rectifier circuit 1
The period t 11 in which V 1 exceeds the detection level V L1 is the time T 1
does not reach. Therefore, timer 3 does not output signal V 3 and timer 4 also does not output signal V 0 .
しかし、第２図の右側に示す期間ロにおいて、
信号Viは電圧VNを超え、信号V1は検出レベル
VL1を超えるので、信号V2は時間T1を超えるパル
ス幅となり、タイマ３は期間t12（＜T2）でハイと
なるパルスの信号V3を出力する。従つて、タイ
マ４は信号V0を出力する。 However, in period B shown on the right side of Figure 2,
The signal V i exceeds the voltage V N and the signal V 1 is the detection level
Since the pulse width exceeds V L1 , the signal V 2 has a pulse width exceeding the time T 1 , and the timer 3 outputs a pulse signal V 3 that becomes high in the period t 12 (<T 2 ). Therefore, timer 4 outputs signal V 0 .
第３図は信号Viにパルス性の雑音が重畳される
場合の動作を説明する波形図である。このような
Viが入力されると、整流回路１の信号V1はその
雑音により検出レベルVL1と交差するものとな
り、検出回路２の信号V2は、期間t13（＞T1）で
ハイを持続するパルスとならず、いわゆる割れ目
を生じ、パルス幅がそれぞれ時間T1以下のもの
になる。従つて、タイマ３は信号V3を出力せず、
装置は誤動作となる。 FIG. 3 is a waveform diagram illustrating the operation when pulse noise is superimposed on the signal V i . like this
When V i is input, the signal V 1 of the rectifier circuit 1 crosses the detection level V L1 due to its noise, and the signal V 2 of the detection circuit 2 remains high for a period t 13 (>T 1 ). Instead, so-called cracks occur, and each pulse width is less than time T 1 . Therefore, timer 3 does not output signal V 3 ,
The device will malfunction.
従来の検出装置は、以上のような構成なので、
入力信号にパルス性の雑音が重畳されると、容易
に誤動作をする欠点があつた。 The conventional detection device has the above configuration, so
It has the disadvantage that it easily malfunctions when pulse noise is superimposed on the input signal.
この発明は、上記のような従来装置の欠点を除
去するためになされたもので、入力信号にパルス
性の雑音が重畳されても容易に誤動作することな
く、信頼性の高い検出が得られる検出装置を提供
することを目的とする。 This invention was made in order to eliminate the drawbacks of the conventional device as described above, and provides a detection system that does not easily malfunction even when pulse noise is superimposed on the input signal and provides highly reliable detection. The purpose is to provide equipment.
以下、この発明の一実施例を図について説明す
る。第４図は、この発明の検出装置の実施例を示
す回路図である。第４図において、第１図と同一
符号の部分は同一部分であることを示し、５は信
号V2を反転させて信号2を出力するインバータ、
６は信号2を入力し、動作時限t〓（例えば２ｍｓ）
及び復帰時限０を有するタイマ、７−１は信号
V2を入力し、そのハイの期間でオンとなるトラ
ンジスタTr1からなるスイツチング回路、７−２
は信号2を入力し、そのハイの期間でオンとな
るトランジスタTr2からなるスイツチング回路、
８−１，８−２はスイツチング回路７−１，７−
２の出力端を互いに逆極性で接続したダイオー
ド、９はダイオード８−１，８−２の接続点とア
ース間に接続され、スイツチング回路８−１のコ
レクタ抵抗RC及びダイオード８−１を介して充
電され、ダイオード８−１及びトランジスタTr2
を介して放電をするコンデンサ、１０はコンデン
サ９の電圧である信号VCTを入力し、検出レベル
VL2を超えた期間で信号V7をハイにする検出回路
で、信号V7をタイマ４の入力信号としている。
抵抗RC及びコンデンサ９により一つの積分回路
が構成される。 An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a circuit diagram showing an embodiment of the detection device of the present invention. In FIG. 4, parts with the same symbols as in FIG. 1 indicate the same parts, and 5 is an inverter that inverts the signal V 2 and outputs the signal 2 ;
6 inputs signal 2 and sets the operation time t〓 (for example, 2ms)
and a timer with a return time of 0, 7-1 is a signal
A switching circuit consisting of a transistor T r1 that inputs V 2 and turns on during its high period, 7-2
is a switching circuit consisting of a transistor T r2 that inputs signal 2 and turns on during its high period,
8-1, 8-2 are switching circuits 7-1, 7-
A diode 9 is connected between the connection point of diodes 8-1 and 8-2 and the ground, and is connected through the collector resistor R C of the switching circuit 8-1 and the diode 8-1. diode 8-1 and transistor T r2
10 inputs the signal V CT which is the voltage of capacitor 9, and sets the detection level
This is a detection circuit that makes the signal V 7 high during a period exceeding V L2 , and uses the signal V 7 as an input signal to the timer 4.
One integrating circuit is constituted by the resistor R C and the capacitor 9.
動作を説明する。第５図は信号Viに雑音が重畳
されない場合の動作を示す波形図である。スイツ
チング回路７−１は、信号2がハイの期間にオ
ンとなり、信号V2と同極性の信号VST1を出力す
る。信号VST1がハイの期間において、コンデンサ
９は、抵抗RC及びダイオード８−１を介して電
圧＋Ｅにより充電される。 Explain the operation. FIG. 5 is a waveform diagram showing the operation when no noise is superimposed on the signal V i . The switching circuit 7-1 is turned on while the signal 2 is high, and outputs a signal V ST1 having the same polarity as the signal V 2 . During the period when the signal V ST1 is high, the capacitor 9 is charged with the voltage +E via the resistor R C and the diode 8-1.
一方、信号2はタイマ６に入力されているの
で、タイマ６は、図示のように信号V2がローに
なつてから時間t〓後にハイとなり、信号V2がハイ
になるとローになる信号V6を出力する。信号V2
がハイの期間でスイツチング回路７−２のトラン
ジスタTr2はオンになるので、コンデンサ９の電
荷はダイオード８−２及びトランジスタ７−２を
介して放電される。 On the other hand, since the signal 2 is input to the timer 6, the timer 6 outputs the signal V which becomes high after a time t〓 after the signal V 2 becomes low as shown in the figure, and which becomes low when the signal V 2 becomes high. Outputs 6 . Signal V 2
Since the transistor T r2 of the switching circuit 7-2 is turned on during the period when T r2 is high, the charge in the capacitor 9 is discharged via the diode 8-2 and the transistor 7-2.
このため、コンデンサ９の信号VCTは、期間イ
において検出レベルVL2を超えず、期間ロにおい
て検出レベルVL2を超えたものとなり、図示のよ
うに信号V7を出力する。信号V7は、タイマ４に
入力され、そのパルスを連続させた信号V0とな
る。 Therefore, the signal V CT of the capacitor 9 does not exceed the detection level V L2 during period A, but exceeds the detection level V L2 during period B, and outputs the signal V 7 as shown. The signal V 7 is input to the timer 4 and becomes a signal V 0 made up of continuous pulses.
第６図は信号Viに雑音が重畳された場合の動作
を説明する波形図である。信号V2は、第３図と
同じように割れた波形となるが、その期間（約１
ｍｓ）は２ｍｓに達しないので、タイマ６は信号
V6をその期間で出力しない。従つて、スイツチ
ング回路７−２の信号VST2は、雑音の存在に影響
されることなく、信号V1が検出レベルVL1を超え
る期間でハイとなる。コンデンサ９は、信号VST1
がハイとなる期間において充電され、信号VST2が
ローとなる期間において放電され、充電を開始し
てから時間T1を経過した時点で検出レベルVL2を
超える。検出回路７はこのような信号VCTによ
り、信号V7を出力し、タイマ４は信号V0を出力
する。 FIG. 6 is a waveform diagram illustrating the operation when noise is superimposed on the signal V i . The signal V 2 has a divided waveform as shown in Figure 3, but the period (approximately 1
ms) does not reach 2ms, timer 6
Do not output V 6 in that period. Therefore, the signal V ST2 of the switching circuit 7-2 becomes high during the period in which the signal V 1 exceeds the detection level V L1 without being affected by the presence of noise. Capacitor 9 connects the signal V ST1
It is charged during the period when the signal V ST2 is high, and discharged during the period when the signal V ST2 is low, and exceeds the detection level V L2 when time T 1 has elapsed since the start of charging. The detection circuit 7 outputs a signal V 7 based on such a signal V CT , and the timer 4 outputs a signal V 0 .
即ち、検出装置は、第６図に示すように信号Vi
にパルス幅が１ｍｓ程度の雑音が重畳されてもそ
の判定動作を正しく実行する。 That is, the detection device detects the signal V i as shown in FIG.
To correctly perform a determination operation even when noise with a pulse width of about 1 ms is superimposed on the signal.
第７図はこの発明の他の実施例を示すブロツク
図である。第７図において、１１は第４図に示す
同一符号の部分よりなるブロツク、１２はブロツ
ク１１の出力信号を反転するインバータ、１３は
インバータ１２の出力を導入し、動作時限T2及
び復帰時限０を有するタイマである。インバータ
１２及びタイマ１３は第４図のタイマ４と等価の
機能を有する。 FIG. 7 is a block diagram showing another embodiment of the invention. In FIG. 7, 11 is a block consisting of parts with the same symbols as shown in FIG. 4, 12 is an inverter that inverts the output signal of block 11, and 13 is an inverter for introducing the output of the inverter 12, and has an operation time T 2 and a recovery time 0. This is a timer with Inverter 12 and timer 13 have functions equivalent to timer 4 in FIG.
以上のようにこの発明によれば、検出対象の入
力信号に雑音が重畳され、波形歪を生じても、そ
れがタイマ６の動作時限以下である限り、誤動作
することはなく、信頼性の高い判定結果が得られ
る効果がある。 As described above, according to the present invention, even if noise is superimposed on the input signal to be detected and waveform distortion occurs, as long as the distortion is within the operating time limit of the timer 6, there will be no malfunction, resulting in high reliability. This has the effect of obtaining judgment results.
第１図は従来の検出装置のブロツク図、第２図
及び第３図は第１図に示す装置の動作の波形図、
第４図はこの発明の一実施例による検出装置の回
路図、第５図及び第６図は第４図に示す装置の動
作の波形図、第７図はこの発明の他の一実施例を
示す検出装置のブロツク図である。
１……整流回路、２，１０……検出回路、３，
４，６，１３……タイマ、７−１，７−２……ス
イツチング回路、８−１，８−２……ダイオー
ド、９……コンデンサ。なお、図中、同一符号は
同一部分を示す。
FIG. 1 is a block diagram of a conventional detection device, FIGS. 2 and 3 are waveform diagrams of the operation of the device shown in FIG.
FIG. 4 is a circuit diagram of a detection device according to an embodiment of the present invention, FIGS. 5 and 6 are waveform diagrams of the operation of the device shown in FIG. 4, and FIG. 7 is a circuit diagram of a detection device according to another embodiment of the present invention. FIG. 3 is a block diagram of the detection device shown in FIG. 1... Rectifier circuit, 2, 10... Detection circuit, 3,
4, 6, 13...Timer, 7-1, 7-2...Switching circuit, 8-1, 8-2...Diode, 9...Capacitor. In addition, in the figures, the same reference numerals indicate the same parts.
Claims (1)
の第１のレベルにより上記整流回路の出力レベル
を検出する第１の検出回路と、この第１の検出回
路の出力により動作する上記信号に重畳された雑
音のパルス幅の時間より長い動作時限t〓及び復帰
時限０を有する第１のタイマと、上記第１の検出
回路の出力が所定の論理レベルにある期間に積分
をし上記第１のタイマの出力が所定の論理レベル
にある期間に放電するコンデンサを有する積分回
路と、この積分回路の出力を上記第１のレベルに
対応した第２のレベルでレベル判定をする第２の
検出回路と、この第２の検出回路の出力により動
作し、所定期間その動作を保持する第２のタイマ
とを備え、上記信号の電気量を弁別する電気量検
出装置。1. A rectifier circuit that rectifies the signal to be detected, a first detection circuit that detects the output level of the rectifier circuit based on a predetermined first level, and a signal that is superimposed on the signal that operates based on the output of the first detection circuit. A first timer having an operation time t which is longer than the pulse width of the detected noise and a recovery time 0, and the first timer are integrated during a period in which the output of the first detection circuit is at a predetermined logic level. an integrating circuit having a capacitor that discharges during a period when the output of the timer is at a predetermined logic level; and a second detecting circuit that determines the level of the output of the integrating circuit at a second level corresponding to the first level. and a second timer that operates based on the output of the second detection circuit and maintains its operation for a predetermined period of time, and discriminates the electrical quantity of the signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7880381A JPH0228832B2 (en) | 1981-05-22 | 1981-05-22 | DENKIRYOKENSHUTSUSOCHI |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7880381A JPH0228832B2 (en) | 1981-05-22 | 1981-05-22 | DENKIRYOKENSHUTSUSOCHI |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57192875A JPS57192875A (en) | 1982-11-27 |
| JPH0228832B2 true JPH0228832B2 (en) | 1990-06-26 |
Family
ID=13672008
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7880381A Expired - Lifetime JPH0228832B2 (en) | 1981-05-22 | 1981-05-22 | DENKIRYOKENSHUTSUSOCHI |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0228832B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6293671A (en) * | 1985-10-18 | 1987-04-30 | Yaskawa Electric Mfg Co Ltd | Low voltage detection circuit |
| FR3085239B1 (en) * | 2018-08-24 | 2020-07-31 | Safran Electronics & Defense | SYSTEM FOR DETECTION OF A DROP IN THE VOLTAGE OF AN ALTERNATIVE POWER SUPPLY |
-
1981
- 1981-05-22 JP JP7880381A patent/JPH0228832B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57192875A (en) | 1982-11-27 |
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