JPH0228849A - Memory device - Google Patents

Memory device

Info

Publication number
JPH0228849A
JPH0228849A JP63179542A JP17954288A JPH0228849A JP H0228849 A JPH0228849 A JP H0228849A JP 63179542 A JP63179542 A JP 63179542A JP 17954288 A JP17954288 A JP 17954288A JP H0228849 A JPH0228849 A JP H0228849A
Authority
JP
Japan
Prior art keywords
address
ibp
ram
register
rom
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63179542A
Other languages
Japanese (ja)
Inventor
Ichiro Yamane
一郎 山根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63179542A priority Critical patent/JPH0228849A/en
Publication of JPH0228849A publication Critical patent/JPH0228849A/en
Pending legal-status Critical Current

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  • Memory System (AREA)

Abstract

PURPOSE:To completely eliminate the change of a program even when the necessity of rearrangement is generated by providing one register and one subtracter and setting a free memory space in correspondence to the scale of a system. CONSTITUTION:An arbitrary address is set to a IBP 1 with initial setting. When a ROM goes to be large and the address of the ROM is overlapped with that of a RAM in a present memory map, such a problem can be solved since the enough memory space can be obtained by causing the value of the IBP 1 to be larger than the present value. Even when the RAM goes to be large, the same processing can be executed. Further more, it can be also to wholly arrange a ROM 6, a RAM 5, a register file 4 and an I/O 3 continuously from an address 0. An unnecessary high order address bit can be made unused. By referring the IBP 1 as the register, it is wholly unnecessary to change the program with the change of the value of the IBP 1.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、マイクロプロセッサ等で、メモリ空間を決定
する際、システムの規模、ROM、RAMの大きさに応
じて自由にメモリ空間を再配置できるメモリ装置に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a memory that allows the memory space to be freely rearranged according to the system scale, ROM, and RAM size when determining the memory space in a microprocessor or the like. It is related to the device.

従来の技術 従来、マイクロプロセッサにおいて、メモリ空間は第3
図に示すようにハードウェア決定時に固定されており、
後に、ROMやRAMの拡張が必要となった際、メモリ
空間の再配置を行う必要があった。この際、それまで構
成されていたハードウェアは再度作り直さねばならず、
また、ソフトウェアも新しいメモリアップにあわせて作
成し直す必要があった。
BACKGROUND OF THE INVENTION Traditionally, in microprocessors, memory space is
As shown in the figure, it is fixed at the time of hardware decision,
Later, when it became necessary to expand the ROM and RAM, it was necessary to rearrange the memory space. At this time, the hardware that had been configured up until then had to be rebuilt,
Also, the software had to be rewritten to accommodate the new memory upgrade.

また、メモリ管理ユニット(以下MMUと略す)を用い
てメモリ空間を自由に設定することも可能である。しか
し、MMU自体のハードウェアは相当大きなものであり
、簡単に実現することは難しく、また実現したとしても
多くの初期設定を必要とした。
Furthermore, it is also possible to freely set the memory space using a memory management unit (hereinafter abbreviated as MMU). However, the hardware of the MMU itself is quite large, so it is difficult to implement it easily, and even if it were implemented, it would require a lot of initial settings.

発明が解決しようとする課題 上記従来の方式ではメモリ空間が決定されているために
ROM、RAMの拡張性に乏しく、プログラムをシステ
ムの大きさにあわせていく必要があった。
Problems to be Solved by the Invention In the above-mentioned conventional system, the memory space is determined, so the expandability of the ROM and RAM is poor, and it is necessary to adapt the program to the size of the system.

また、MMUを用いた場合、ハードウェアが大きいため
にコスト面等から問題があった。
Furthermore, when an MMU is used, there are problems in terms of cost and the like because the hardware is large.

課題を解決するための手段 この目的を達成するために、本発明では入出力ベースポ
インタまたは設定可能なレジスタとアドレスから上記レ
ジスタの内容を減する減算器とを持ち、その減算された
値を新しいアドレスとして、各周辺回路、メモリ回路等
を配置することができるようにしたものである。
Means for Solving the Problems To achieve this object, the present invention has an input/output base pointer or a settable register and a subtractor that subtracts the contents of the register from the address, and the subtracted value is used as a new Each peripheral circuit, memory circuit, etc. can be placed as an address.

作用 このようにすれば、簡単な初期設定を行うだけで、シス
テムの大きさに応じて自由にメモリ空間を決定できる。
Effect: By doing this, you can freely determine the memory space according to the size of the system by just making simple initial settings.

実施例 以下、本発明の実施例について図面を参照しながら説明
する。
EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

第1図は、本発明の一実施例における構成ブロック図で
ある。
FIG. 1 is a configuration block diagram in one embodiment of the present invention.

この図で、1は入出力ベースポインタ(IloBPまた
はIBP)としての設定可能なレジスタ(以下IBPと
略す)であり、2はアドレスからIBPIの値を減する
減算器であり、l103゜レジスタファイル4.RAM
5は減算された値を新しいアドレスとして、メモリ空間
に配置されている。また、ROM6はアドレスに直接配
置されている。
In this figure, 1 is a register (hereinafter abbreviated as IBP) that can be set as an input/output base pointer (IloBP or IBP), 2 is a subtracter that subtracts the value of IBPI from the address, and l103° register file 4 .. RAM
5 is placed in the memory space using the subtracted value as a new address. Further, the ROM 6 is arranged directly at the address.

まず、初期設定として、IBPIに任意のアドレスが設
定される。この時のメモリマツプの一例を第2図に示す
。ROM6は、IBPに全く関係なく、アドレスOより
配置され、l103.レジスタファイル4.RAM5は
IBPIの値を中心に配置されている。
First, as an initial setting, an arbitrary address is set in IBPI. An example of the memory map at this time is shown in FIG. ROM6 is located from address O, regardless of IBP, and from l103. Register file 4. The RAM 5 is arranged around the value of IBPI.

いまここで、ROMが大きくなったために、現在のメモ
リマツプではRAMとアドレスが重なってしまう場合が
生したとする。するとIBPIの値を現在よりも大きく
することによって十分なメモリ空間がとれるので解決で
きる。また、RAMが大きくなったときも同様である。
Suppose now that because the ROM has become larger, a case has arisen in which addresses overlap with the RAM in the current memory map. The problem can then be solved by increasing the IBPI value to a larger value than the current value, since sufficient memory space can be secured. The same applies when the RAM becomes larger.

しかも、このメモリマツプ例では、ROM6.RAM5
.レジスタファイル4.l103をすべてアドレスOか
ら連続的に配置することも可能であり、不用な上位アド
レスビットを未使用にすることも可能である。例えば6
4にバイトに収まった場合は下位16ビツトのアドレス
だけを用いればよい。
Moreover, in this memory map example, ROM6. RAM5
.. Register file 4. It is also possible to arrange all of l103 consecutively starting from address O, and it is also possible to leave unnecessary upper address bits unused. For example 6
If the address fits within 4 bytes, only the lower 16 bits of the address need to be used.

また、IBPIをレジスタとして参照できるようにする
ことによって、l103.レジスタファイル4等をIB
PI相対でプログラムを作成することができ、これによ
って上記IBPIの値の変更によるプログラムの変更は
全く不要とすることができる。
Also, by allowing IBPI to be referenced as a register, l103. IB register file 4 etc.
A program can be created relative to the PI, thereby making it completely unnecessary to change the program by changing the IBPI value.

発明の効果 以上のように本発明は、1つのレジスタと1つの減算器
を設けることによって、システムの規模に応じて自由な
メモリ空間を設定でき、再配置の必要が生じた際もプロ
グラムの変更は全(不要にすることができる。
Effects of the Invention As described above, by providing one register and one subtracter, the present invention allows free memory space to be set according to the scale of the system, and even when relocation is necessary, the program can be changed easily. is all (can be made unnecessary.

【図面の簡単な説明】[Brief explanation of the drawing]

1・・・・・・設定可能なレジスタTBP、2・・・・
・・アドレスからIBPの値を減する減算器、3・・・
・・・Ilo、4・・・・・・レジスタファイル、5・
・・・・・RAM、6・・・・・・ROM。
1...Settable register TBP, 2...
...Subtractor that subtracts the value of IBP from the address, 3...
...Ilo, 4...Register file, 5.
...RAM, 6...ROM.

Claims (1)

【特許請求の範囲】[Claims] 入出力ベースポインタまたは設定可能なレジスタと、ア
ドレスから上記レジスタの内容を減算する減算器とを持
ち、その減算された値を、新しいアドレスとして各周辺
回路、メモリ回路を配置することのできるメモリ装置。
A memory device that has an input/output base pointer or a configurable register and a subtracter that subtracts the contents of the above register from the address, and can use the subtracted value as a new address to allocate each peripheral circuit and memory circuit. .
JP63179542A 1988-07-19 1988-07-19 Memory device Pending JPH0228849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63179542A JPH0228849A (en) 1988-07-19 1988-07-19 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63179542A JPH0228849A (en) 1988-07-19 1988-07-19 Memory device

Publications (1)

Publication Number Publication Date
JPH0228849A true JPH0228849A (en) 1990-01-30

Family

ID=16067571

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63179542A Pending JPH0228849A (en) 1988-07-19 1988-07-19 Memory device

Country Status (1)

Country Link
JP (1) JPH0228849A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020125457A (en) * 2019-02-01 2020-08-20 ハンコック タイヤ アンド テクノロジー カンパニー リミテッドHankook Tire & Technology Co., Ltd. Adhesive composition and method for producing non-pneumatic tire using the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61245259A (en) * 1985-04-23 1986-10-31 Nec Corp Address control circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61245259A (en) * 1985-04-23 1986-10-31 Nec Corp Address control circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020125457A (en) * 2019-02-01 2020-08-20 ハンコック タイヤ アンド テクノロジー カンパニー リミテッドHankook Tire & Technology Co., Ltd. Adhesive composition and method for producing non-pneumatic tire using the same
US11814551B2 (en) 2019-02-01 2023-11-14 Hankook Tire & Technology Co., Ltd. Adhesive composition and method of manufacturing nonpneumatic tire by using same

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