JPH0228863A - Inter-cpu data transfer system - Google Patents

Abstract

PURPOSE:To transfer a large quantity of data at high speed by providing a selector to attain access from two CPUs and controlling its direction from the system board of the CPU which is a master. CONSTITUTION:A signal line 9 is controlled and memories 51 and 52 are replaced from under microprocessors (MPU) 1 and 2 to under the contrary MPUs 2 and 1 respectively. The memory of the MPU 1 consists of memories 121, 131 and 51 and the memory of the MPU 2 consists of memories 122, 132 and 52. When the memories are interchanged, the MPU 1 operates to access the memory 52, the MPU 2 operates to access to the memory 122 and the memory used by the other side CPU can be accessed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a system for exchanging information between CPUs in a device equipped with a plurality of CPUs, and particularly relates to a system for transferring large amounts of data at high speed. .

(Prior art) Conventionally, this type of data transfer between CPUs
I10 transfer of data using the serial I10° or paran IMI10, which is a peripheral device of the U, has been successfully adopted. In the above, each CPU writes necessary information from its own memory to the device, and receives information sent from the other party from its own I10 device to its own memory.
A second method is known in which a dual port memory is provided as a common memory between CPUs and mutually read and write from and to the memory.

(Problem to be Solved by the Invention) The first conventional I10 transfer method described above extracts data in bytes from memory, transmits it using an I10 device, and receives data from the other party's memory from the I10 device in the same way. method, it is always necessary to transfer large amounts of data.
Both CPUs have no choice but to intervene. Therefore, it is necessary to allocate a large amount of processing by the CPU to the current work, and there is a drawback that it is unsuitable for high-speed transfer of large amounts of data.

The second method using the conventional dual port memory UK has the disadvantage that large-scale memory capacity becomes expensive because large-capacity devices are not available.Also, although it is a dual port, simultaneous access to the same address is not possible. There were drawbacks, such as having to wait for a meeting. .

An object of the present invention is to provide control signals for memory read/write, etc.
Providing a selector to enable access from both CPUs for addresses and data, and controlling this direction from the system port of the master CPU, eliminates the above disadvantages and allows large amounts of data to be processed at high speed. It is possible to configure it so that it can be transferred and to provide an inter-CPU transfer method. .

(Means for Solving the Problems) The CPU-to-CPU data transfer method according to the present invention includes two CPUs, a pair of memories, a - type selector, and a system board/lotus. .

The two CPUs operate as master and slave,
It is a turtle for sending and receiving large amounts of data. .

The pair of memories are for use as switching memories by each of the two CPUs. .

The - type selector is used to mutually switch control signals, addresses, and data to the corresponding memory to the other CPU based on instructions from the master CPU.

The system port/pass is used to import the contents of the memory corresponding to the CPU of the other party into its own memory space, and to transmit and receive large amounts of data at high speed. .

(Example) Next, one embodiment of the present invention will be explained with reference to the drawings. .

FIG. 1 is a block diagram showing an embodiment of an inter-CPU data transfer method according to the present invention. .

In Figure 1, 1.2 each has nine microprocessor units (9 microprocessor units) each containing a CPU that requires data transfer.
Here, the microprocessor unit 1 is expressed as the master side. , 31 and 32 are address buses for transferring memory read/write control signals and address information sent from each microprocessor 1 and 2, respectively, and 41 and 42 are data buses, respectively. , Sl, and S2 are memories that can be exchanged with each other. , 6 j , 62 are selectors, respectively, and memory blocks 151.82
Of the address signals etc. input to the address bus 31
The signal on the address bus 32 or the signal on the address bus 32 is selected. , 7. ．． 1 and 72 are bidirectional selectors, respectively, data bus 41, and data bus 4
1 connected to selector 61.62.2. F1. The selection signal for F2 is output from the first bit of the system port 81 on the master side via the signal line 9.

Notes for 10.11 from system boats 81 and 82 respectively! In order to confirm the exchange of Jgl and 82, an example of the method of transmitting and receiving control signals on the control signal lines 1 and 1 (1 and 11, which are the control signal lines used between the CPUs, will be explained in detail in Fig. 8, which will be described later). , 121, 122, 131, and 132 are memories owned independently by each microprocessor 1 and 2, and the memory map is explained in Figure 2. In this case, rather than controlling the signal line 9, the memories 51 and 82 are connected to the reverse MPU from under the microprocessor unit 1.2.
It becomes possible to change the subordinate Kfil.

FIG. 2 is a CPU memory map, which is a turtle showing how the memory shown in FIG. 1 is replaced.

The memory of microprocessor unit (MPU1) 1 is M
I 1 , Ml 2 , Ml 8, and the microprocessor unit (MPU2) 2 is M21. M2R, M
Let's say a turtle is made up of 2Rs. The entire space is an MPU
Although it is not necessary for MPU2 to have the same capacity, memory MI2.I and MPU2 are the target of replacement. FII! 22 must logically have the same space capacity. .

However, even in this case, the absolute addresses do not need to match 1. When memory is exchanged, the memories on the memory map are swapped from left to right as shown in Figure 2.
, that is, MPU1 accesses memory M22 and MPU1 accesses memory M22.
PU2 operates to access memory M21,
It becomes possible to access the memory used by the other party's CPU. .

Therefore, with the above, it is possible to transfer data between CPUs at the block level1.If memory exchange is performed without any prior notice, a button handquake is required to prevent each CPU from going out of control1. , FIG. 8 is an explanatory diagram showing an example of the handshake. 1. The system boat signals on signal lines 9 to 11 in FIG. 1 correspond to handshake signals. 1. First, the transmission data is When data processing is executed, the master CPU 1 sends a request (REQ) signal to the signal line 11 and opens the system of the MPU 2. M
The aMPUI sends an acknowledgment to the PUI.
When it receives K, it sends a path switching signal to the selectors 61, 62 and F1, 72 via the signal line 9. At the same time, M.P.
U1 sends an EXE signal on the signal line 9 indicating that switching is in progress, and becomes K when the same procedure is followed to restore the switching.

If the button needs to be executed based on a request from the slave side, just increase the number of control signal lines.
This allows the slave side to send the REQ signal to the master side, and repeat the same procedure on the master side. Such a procedure is just an example, and it goes without saying that known methods such as sending and receiving control signals on a character basis can be used for confirmation.

(Effects of the Invention) As explained above, the present invention allows a large amount of information to be transferred to the other party's CPU while being stored in memory, rather than exchanging memory addresses/data for each pass. This has the effect of allowing data to be transferred to. As a result of this K, the time allocated to each CPU for communication becomes extremely short, and there is an effect that the data processing capacity after transfer is improved by several steps.

Furthermore, since the memory used in the present invention is a normal random access memory, the capacity can be increased arbitrarily, and the effect is that efficient data transfer is possible without using expensive dual-port memory. be,.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the RCPU-to-RCPU data transfer method according to the present invention. FIG. 2 is an explanation showing the transition of the memory map in the embodiment of the present invention shown in FIG. It is a diagram. FIG. 8 is an explanatory diagram showing the procedure of memory switching. FIG. 4 is a block diagram showing an example of a communication method using a conventional I10 device. . 1.2--Microprocessor unit 31.32--
・Address bus 41.42...-Data bus! 51.82, 121.122, 131.132...
...Memory 61.62. F1. F2...Selector 81.82...
・System ports 141, 142...I10 devices 9 to 11---Signal lines Figure 3 (Mastan Figure 24)

Claims (1)

[Claims] Two CPUs that operate as a master and a slave to transmit and receive large amounts of data, a pair of memories that are used as switching memories by each of the two CPUs, and a corresponding memory that is configured according to instructions from the master CPU. A set of selectors for switching control signals, addresses, and data to the memory to each other CPU, and the content of the memory corresponding to the other CPU is imported into the own memory space, and a large amount of data can be processed at high speed. An inter-CPU data transfer method characterized by comprising a system port/bus for sending and receiving data.