JPH02288919A - Memory device - Google Patents

Abstract

PURPOSE:To sufficiently display the capability of a CPU even at the time of using a memory of low operation speed by writing data in a high-speed register in a memory block after storing it in the high-speed register at the time of writing data from the CPU in the memory block. CONSTITUTION:Plural high-speed registers 12 whose processing speed corresponds to that of a CPU 11 are provided, and a memory block 13 is provided after high-speed registers 12. Though the processing speed of the memory block 13 is low, data in the memory block 13 is stored in high-speed registers 12 to transfer data at a high speed in accordance with the processing speed of the CPU 11 at the time of inputting data to the CPU 11. When requested data is entered in high-speed registers 12, the memory block 13 is not read, and therefore, the data read speed is increased. Thus, the CPU of high speed is used to perform the processing at a high speed though a memory of low speed is used as the memory block.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device in which high-speed registers are connected to memory input and output so that the CPU (Central Processing Unit) of a computer can operate faster.

[Conventional technology]

Conventionally, when a computer's CPU operates faster, a memory element whose memory element itself operates faster has been connected to the CPU to cope with this problem.

[Problem that the invention seeks to solve]

However, fast-acting memory is expensive, and when used in a normal computer, the problem is that the entire system becomes expensive.

The present invention was developed in view of the above circumstances, and it is possible to use a CPU with extremely high speed even when using memory with a slow operating speed.
An object of the present invention is to provide a memory device that can exhibit the ability of the present invention to shorten the overall processing time, and also to reduce the price.

[Another means to solve the problem] A memory device that meets the second purpose is a memory device that stores data and
It has a plurality of high-speed registers having a processing speed corresponding to the PU, a memory block connected to each of the high-speed registers, and an address control device that controls the memory blocks and the high-speed register, and the address control device includes: ,
If the data specified in the high-speed 1/sister is not stored in response to a read signal from the CPU, the data is simultaneously read from the plurality of memory blocks and written in each high-speed register, and the data is stored in each high-speed register. Outputs the specified data from the register, and if the data is stored in the high-speed register for the above-mentioned readout, the data is read from the corresponding high-speed register without reading from the memory drive 1:1. When writing the data from the CPU to the memory block, the control means stores the data in a high-speed register connected to the memory block, and then writes the data in the high-speed register to the memory block. has been done.

Here, memory blocks and high-speed registers are usually cp
Usually, the number is 2N to match the control of u, but
The present invention is not necessarily limited to this number.

[Effect]

In the memory device according to the present invention, a plurality of high-speed registers having a processing speed corresponding to the CPU are provided, and the memory flocks are provided via the high-speed registers, so even if the low-speed memory flocks are low-speed , the data of the memory block is stored in a high-speed register.
When inputting data to the CPU every time, the data can be transferred at high speed according to the processing speed of the CP tJ. If the requested data is written in the high-speed register, reading from the memory block is not performed, so the data can be read at a correspondingly high speed.

Also, when writing data from the CPU to a memory block, a high-speed register that can handle the processing speed of the CPU is provided, so data is written to the high-speed register, and then data is written from the high-speed register to the memory block. It is possible to assign CP[J to a memory block with a lower speed depending on the operation.

〔Example〕

Next, embodiments embodying the present invention will be described with reference to the accompanying drawings 1 to 7, to provide an understanding of the present invention.

Here, FIG. 1 is a schematic configuration diagram of a memory device according to a first embodiment of the present invention, FIGS. 2 and 3 are flow diagrams showing the operating state of the memory device, and FIG. Schematic configuration diagram of the memory device according to the second embodiment, FIGS. 5 and 6
The figure is the memo'J l! FIG. 7 is a plan view showing connection terminals in the case where a position is arranged in one chip.

As shown in FIG. 1, a memory device 10 according to the first embodiment of the present invention includes eight high-speed registers 12 connected to a CPU 1 and a state memory RAM connected to the high-speed registers 12. 8 memory blocks 1
3, and the high speed register 12 and memory block 11
The address control device 14 controls the address control device 14.

For the high-speed register 12, a high-speed element having a processing speed approximately equal to the processing speed of the CPU 11 is selected, and for the memory block 13, a static RAM that operates at a normal slow speed is selected. It consists of

Since instructions for controlling the memory block 13 and high-speed register 12 are written in the address control device 14, these instructions will be explained with reference to FIGS. 2 and 3.

First, when reading data in the a-memory block 13, as shown in FIG. 15) If writing has been performed, write the data in the predetermined high-speed register 12 to the memory (step 16), set the memory read address (step 17), and read the data from the memory block 13. In step 18), set the data in the high-speed register 12, increment the read-ahead address, and set the address next to the read memory number 1 as cents.
(Step 19). As a result, the next data can be placed in a standby state without setting the address of the memory block 13 again, and the data can be read from the memory block 13 to the high-speed register 12, so that high-speed processing can be performed.

Thereafter, the CPU 11 reads the data in the high-speed register 12 (step 20), but since the processing speed of the high-speed register 12 is fast, the data can be taken into the CPU 11 in a short time.

Next, if the data has not been previously written, it is determined whether or not the data exists in the high-speed register 12 (step 21); if the data exists, the data is read out in step 20.

Here, if there is no data in the high-speed register 12, it is determined whether or not the memory pre-reading has been completed (step 22), and if the memory pre-reading has not been completed, the process of steps 17 to 20 is performed. High speed register 1
Read the data from 2.

In the above process, if the pre-reading of the memory has been completed, it is determined whether the pre-read address and the requested address match (step 23), and if they match, the data is transferred to the high-speed register 12. At the same time, the pre-read address is incremented (step 19).
), reads out the data set in the high speed register 12 (step 20).

Here, if the pre-read address and the requested address do not match, the data will be read through the steps 17 to 20. Therefore, in this embodiment, the data is transferred from the memory block 13 to each high-speed register 12. After that, the high-speed register 12 specified by the address output from the CPU 11
Output data from.

When reading data at consecutive addresses, if the data is already stored in the high-speed register 12, the data is output from the high-speed register 12 without reading from the memory block 13. And CPUI
1 reads data from the high-speed register 12, data from the memory block 13 at the next address is read from the memory block 13. In this embodiment, when reading data from consecutive addresses, the first memory block 13 is read.
There is no need to slow down the operation of the CPU 1 by simply slowing down the operation of the CPU II when reading the memory block 13 or when reading the memory block 13 for the second time, and the read-ahead address is incremented for subsequent reads.

With the conventional method, each time a memory read is performed,
Although it is necessary to slow down the operation of the CPU in accordance with the operation time of the memory, this point has been improved in this embodiment.

Note that when reading or writing to the memory block 13 is executed, or when reading from a block other than the block being pre-read is requested, the pre-read processing is canceled and read from the memory again, and the data is stored in the high-speed register 12. outputs a BUSY signal to delay the operation of CPLJII.

Next, the case of writing data to the memory block 13 will be explained with reference to FIG.
When there is a write command from I, first, it is determined whether or not writing was performed last time (step 24), and if writing was not performed last time, a write (WRITE) address is set (step 25), and the high-speed Data is set in the register 12 (step 26).

If there is a previous write command, it is determined whether the write address from the CPU 11 and the write I address match (step 27), and if they match, the process directly proceeds to step 26. High speed register 1
Set the data to 2.

On the other hand, if the write address from the CPU II and the write address do not match, after writing the data in the high speed register 13 to the memory block 13 (step 28), set the write address and write the data to the high speed register 13. Seso I-Do (Steps 25-26)
.

Therefore, in this embodiment, when writing data to the memory block 13, the data is stored in the high speed register 12 and then written to the memory block 13. When writing data continuously, data for blocks connected in parallel is stored in high-speed register J.
2 and then written to the memory block 13.

Note that when writing data from the high-speed register 12 to cPL, Jtt, Cl) 1. Although it is not necessary to slow down the operation of J11, when writing from the high-speed register 12 to the memory block 13, the BtJSY signal is output to slow down the operation of the CPU.

FIG. 4 shows a memory device 2 according to a second embodiment of the present invention.
9 is an example in which the present invention is applied to a dynamic RAM, in which the data in the memory block 30 consisting of the dynamic RAM of the RAS address manually entered along with the RAS signal is read out using the CAS signal, and the first read register consisting of a high-speed register is read out. 31 and then transferred to a second read register 32 consisting of a high speed register. After this, the data specified by the CAS address is transferred to the second
It is output from the read register 32 of. When performing this process, it is necessary to delay the operation of the CPU (not shown), so a BUSY signal is output from the address control device 29a.

When reading data from consecutive addresses, use CA
Since the focus data specified by the S address is output, reading of the memory block 30 consisting of a dynamic RAM is not performed.

When writing data to the memory block 30, the data is written to the bits of the write register 33, which is a high-speed register specified by the CAS address, and then the data is written to the memory block 30.

When writing data to consecutive addresses, the data is written to the write register 33 in succession, and when the address range is exceeded, the data is written to the memory block 30 consisting of a dynamic RAM. When performing this, it is necessary to delay the operation of CPtJ, so a BUSY signal is output.

Note that CLOCK in FIGS. 1 and 4 is input to create timing for write/read control.

FIG. 5 shows a memory device 10 according to an embodiment of the present invention.
This is an example of a signal line when stored in a chip IC, and unlike conventional static memory, a new BUS
A Y signal is added. This BUSY signal is output in the cycle in which data is read from the memory block and transferred to each high-speed register, and in the cycle in which data is written from the high-speed register to the memory block.
When this output is output, it is necessary to delay the operation of the CPU.

The invention according to this embodiment can also be applied to read-only memories.

FIG. 6 shows an example of the signal lines of an IC in which the memory device 29 is housed in one chip, and unlike the conventional dynamic memory, a new 13 U S Y signal is added. This BtJSY signal is output during the cycle when data is transferred from the memory block consisting of dynamic RAM to the high-speed register, and during the writing of data from the high-speed register to the memory block, and adjusts the CPU operation to the speed of the memory block. and delay it.

Note that although the examples shown in FIGS. 5 and 6 both have a built-in CLOCK generation circuit for timing control, the present invention applies even if the CLOCK generation circuit for control is external. is applicable.

In addition, in FIGS. 5 and 6, one chip of IC
Although the memory device is incorporated in the present invention, the present invention is also applicable to implementation on a printed circuit board using conventional memory devices.

〔Effect of the invention〕

According to the present invention, even if a slow memory is used in a memory block, a high-speed CPU can be used and processing can be performed at high speed.

Therefore, there is no need to use expensive memory, and the overall cost of the device can be reduced.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a memory device according to a first embodiment of the present invention, FIGS. 2 and 3 are flow diagrams showing the operating state of the memory device, and FIG. 4 is a schematic diagram of a memory device according to a first embodiment of the present invention. The schematic configuration diagram of the memory device according to the embodiment, and FIGS. 5 and 6 are plan views showing connection terminals when the memory device is arranged in one chip. [Explanation of symbols] 10--------Memory device, 11 ---CP
U. 12 ・---1---High speed register, 13------
Memory block, 14 -1111 Address control device, 29-1 Memory device, 29 a---
-Address control device, 30--------Memory block, 31 -m-----First read register (high speed register), 32 Second read register, 33
−−−−−−−One write register (high-speed register) Agent Patent attorney Fujio Chubu

Claims (2)

[Claims] (1) It has a plurality of high-speed registers that store data and have a processing speed corresponding to the CPU, memory blocks each connected to the high-speed registers, and an address control device that controls the memory blocks and the high-speed registers. ,
The address control device simultaneously reads data from the plurality of memory blocks and stores it in each high-speed register when the data specified in the high-speed register is not stored in response to a read signal from the CPU. , output specified data from each high-speed register, and if data is stored in the high-speed register in response to the read signal, output the data from the corresponding high-speed register without reading from the memory block. When outputting and writing data from the CPU to a memory block, the controller has control means for storing the data in a high-speed register connected to the memory block and then writing the data in the high-speed register to the memory block. A memory device featuring: (2) The memory device according to claim 1, comprising 2^N memory blocks and high-speed registers.