JPH02288924A - High-speed memory access control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding a high-speed memory access control method in image data processing, the present invention enables high-speed access in both the main scanning direction and the sub-scanning direction to a memory composed of the minimum necessary memory chips. With the aim of achieving In a memory access control method comprising a memory access means, each pixel is assigned to a different memory chip in the main scanning direction and the sub-scanning direction, and generation of a predetermined address is controlled corresponding to each scanning direction. The system is configured to include a control means for performing the following.

[Industrial application field]

The present invention relates to a high-speed memory access control method in image data processing.

In recent years, as the speed of image data processing has increased, there has been a demand for faster readout not only in the main scanning direction but also in the sub-scanning direction in memory access.

[Conventional technology]

The memory to which memory chips are allocated to each pixel can be configured with the minimum necessary memory chips corresponding to the number of bits accessed in the same cycle. That is, for example, to read 16 bits (1 word) of data, the same address of 16 memory chips (o, 12, . . . , E, F) corresponding to each bit is accessed. .

FIG. 4 shows that in a bitmap image array, 1
1 is a diagram illustrating an example of the arrangement of a conventional memory chip that enables word access; FIG.

In the figure, symbols 0 to F indicate memory depth numbers in hexadecimal notation.

When reading data in each block (16 bits) in the same cycle, the address input to each memory chip is [vertical address (y) horizontal address (X)] (binary representation, the same applies hereinafter).

That is, in memory access in the main scanning direction, when reading data in block Y1 of the first line, (χ,
Since y)=(1,0), [01] is input to each memory chip from 0 to F as an access address. Similarly, when reading the data of block Y2 on the second line, since (x, y) = (0, 1),
Input [101 as an access address to each memory chip from 0 to F.

[Problem to be solved by the invention]

By the way, in the conventional arrangement of memory chips, each pixel is assigned to the same memory depth in the sub-scanning direction, so access in the same cycle is impossible.

Therefore, for example, when reading 16-bit data in the sub-scanning direction, each block in the main-scanning direction containing the corresponding pixel is accessed 16 times, read out, and added to the 16-bit data in the sub-scanning direction. was necessary.

Note that Japanese Patent Application Laid-Open No. 59-186057 (Access Processing Method in Image Memory System) discloses a method for accessing image data at high speed. As the speed increases, the burden on the control system increases.

An object of the present invention is to provide a high-speed memory access control method that enables high-speed access in both the main scanning direction and the sub-scanning direction in a memory configured with the minimum necessary memory chips.

[Failure to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, the memory 11 has, as a minimum unit, memory chips corresponding to the number of bits accessed in the same cycle.

The memory access means 13 generates an address corresponding to each scanning direction for a memory chip assigned to each pixel.

The control means 15 performs a process of allocating each pixel to a different memory chip in the main scanning direction and the sub-scanning direction, and controls generation of a predetermined address corresponding to each scanning direction.

[For production]

According to the present invention, each pixel in the main scanning direction and the sub-scanning direction is assigned to a different memory chip, at least for bits that are accessed in the same cycle, so it is possible to access each scanning direction in the same cycle. Therefore, it is possible to easily speed up memory access.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

Figure 2 shows that in a bitmap image array, 1
FIG. 3 is a diagram illustrating an example of the arrangement of memory chips according to the invention that allows word access;

In the figure, symbols 0 to F indicate memory chip numbers in hexadecimal notation.

This arrangement example shows a state in which one memory chip is periodically shifted for each line. Note that if the configuration is such that each pixel is not assigned to the same memory chip in the sub-scanning direction, access in the same cycle is possible, so the arrangement is limited to a regular shift arrangement as shown in Figure 2. It's not a thing.

When reading data in block units (16 bits) in the main scanning direction in the same cycle, the address input to each memory chip is [vertical address (y
) horizontal address (X)].

That is, for block Y on the first line, (x
, y)=(LO), and the address input to each memory chip is [01. Furthermore, for block Y2 on the second line, (x, y)=(0, 1), which similarly becomes [10].

Here, when reading data in units of blocks (16 bits) in the sub-scanning direction in the same cycle, the address input to each memory chip is [Vertical address (y) Memory chip number subjected to a predetermined shift amount] Horizontal address (
(upper bits of X corresponding to the block number)].

That is, for block T in the sub-scanning direction, (X
, y) -(00000, Since the shift amount of the IL memory chip number is 0, the address input to the memory chip with memory chip number 0 (referred to as 0 chip, hereinafter the same) is [100000]. , I, 2. 3...., E
, The address input to the F chip is [100010-co[100100] [10011-main] [111100-co[111110].

Furthermore, for block T2 in the sub-scanning direction, (x, y
) = (0001.O), and the shift amount of the memory chip number is 1, so the address input to chip 0 is [0111,10]. Similarly, 1, 2. ..., the addresses input to the F chip are [000000] [000010] [011100].

Furthermore, for block T3 in the sub-scanning direction, (x, y
) - (±0000, 1), and the shift amount of the memory chip number is 0, so the address input to the 0 chip is [100001]. Similarly, 1, 2. ..., the address input to the F chip is [10001 above] [10010 above] [11111].

Furthermore, for block T4 in the sub-scanning direction, (x, y
)-(upper 0001.O), since the shift amount of the memory chip number is 1, the address input to chip 0 is [01111 Sat]. Similarly, 1, 2. ..., the addresses input to the F chip are: co oooo top] [00001 top] [01110 top].

Note that the memory chip arrangement of the bitmap image array shown above can be easily realized using a ring buffer that performs periodic bit shifts.

FIG. 3 is a block diagram showing an example of a device configuration for realizing the method of the present invention.

In the figure, a memory 31 is connected to a system lot 35 via a ring buffer 33. The control circuit 37 extracts the shift amount of the ring buffer 33 from the address data, and sends the access address to the memory 31 and the shift amount to the ring buffer 33, respectively.

Note that the shift amount of the ring buffer 33 is determined by assigning the lower bits of the vertical address in the case of access in the main scanning direction.
If the access is in the sub-scanning direction, it is the lower pix of the horizontal address)
・Assign.

Further, the designation of the main scanning direction or the sub-scanning direction is performed according to a main/sub scanning determination control signal given from the outside.

〔Effect of the invention〕

As described above, according to the present invention, a predetermined number of bits in each scanning direction can be accessed in the same cycle with a simple configuration. Therefore, in image data processing, it becomes easy to speed up reading particularly in the sub-scanning direction, which is extremely useful in practice.

[Brief explanation of drawings]

Figure 1 is a block diagram of the principle of the present invention. Figure 2 is a diagram showing an example of the arrangement of memory chips according to the present invention in a focus map image array. Figure 3 is an example of a device configuration for realizing the method of the present invention. Block Diagram FIG. 4 is a diagram showing an example of the arrangement of conventional memory chips in a bitmap image array. In the figure, 11 is a memory, 13 is a memory access means, and 15 is a control means.

Claims (1)

[Claims] (1) A memory (11) that has memory chips corresponding to the number of bits accessed in the same cycle as the minimum unit, and a memory that generates addresses corresponding to each scanning direction for the memory chips assigned to each pixel. In the memory access control method, the memory access control method includes an access means (13), in which each pixel is assigned to a different memory chip in the main scanning direction and the sub-scanning direction, and a predetermined address is assigned to each pixel in the main scanning direction and in the sub-scanning direction. A high-speed memory access control method characterized by comprising a control means (15) for controlling generation.