JPH02289086A - Image processor - Google Patents

Abstract

PURPOSE:To constitute this processor so that all memories can be used for a main memory and a frame memory, and also, the respective sizes can be varied by placing physically the main memory and the frame memory on the same address space. CONSTITUTION:To a fame controller 6, a common memory 10 is connected, and it is connected to an interface 8 to a printer body or a display device body. The memory 10 can be used for both a main memory and a frame memory, and as for this memory, the main memory and the frame memory are not discriminated, placed on the same address space, and constituted so that all locations of the memory 10 can be allocated in any way. In such a way, in accordance with necessity, a main memory size and a frame memory size can be varied, it is possible to cope with a page size fluctuation and a frame size fluctuation, and the memory can be used efficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to image processing devices such as printers and CRT display devices.

Conventional technology FIG. 3 shows the electrical configuration of a conventional image processing device.

The image processing device has a central processing unit (CPU) that controls the entire image processing device.
) (1), which includes a ROM (2), a character generator (CG) (3) a main memory (or work memory) (4), and a host interface (5).
) and frame control (6) are connected. A frame memory (or bitmap memory) (7) is connected to the frame control (6), which is further connected to the printer body or the display device body via an interface (8).

Program data is stored in ROM (2).

The main memory (4) normally stores received data, page data, etc. written from the CPU (1).
The written data is read out as is.

The frame memory (7) is used for writing and reading data that has undergone bit handling such as data shifting and logical operations.

Frame control (6) is for controlling data shifting, logical operations, etc.

FIG. 4 shows the relationship between the CPU address space, main memory, and frame memory of such a conventional image processing apparatus.

Main memory and frame memory are physically separated depending on their purpose, and each memory size is fixed. When memory is accessed in the CPU address space (main), only the main memory can be accessed.
When memory is accessed in the CPU address space (frame), only the frame memory can be accessed.

Problems to be Solved by the Invention In general, in image processing devices, the size of the main memory and frame memory fluctuates depending on the usage status (page size fluctuation, frame size fluctuation, etc.), and both have empty areas, A shortage area occurs. Therefore, it is necessary to set both memories to the maximum size so that the usage size of each memory may fluctuate, and normally there is a large amount of free space, resulting in wasted memory.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and provide an image processing device in which all memories can be used as a main memory and a frame memory, and the sizes of each can be changed.

Means for Solving the Problems An image processing apparatus according to the present invention includes a main memory for storing program data, received data, page data, etc., and a main memory for storing bit patterns.
An image processing apparatus having a frame memory is characterized in that the main memory and the frame memory are physically arranged in the same address space.

Function Since main memory and frame memory are physically located in the same address space, any memory address can be accessed as either main memory or frame memory. Therefore, there is no boundary between main memory and frame memory, and there is no need to fix the main memory size and frame memory size. Therefore, the main memory size and frame memory size can be changed as necessary, and it is possible to cope with page size fluctuations and frame size fluctuations, and to use memory efficiently.

Embodiment Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1 and 2.

Figure 1 shows an example of the electrical configuration of an image processing device;
The same parts as in the conventional example in the figure are given the same reference numerals.

CPU (1) has ROM (2), CG (3)
, host interface (5) and frame control (7)
) are connected. Then, in frame control (7),
A common memory (10) is connected, and this is an interface (8) with the printer body or display device body.
It is connected to the.

Memory (10) can be used as both main memory and frame memory, which means that main memory and frame memory are physically located in the same address space without distinction, and that all locations of memory (10) can be used as both main memory and frame memory. can be allocated in any way.

FIG. 2 shows the relationship between the CPU address space and memory of the above image processing apparatus.

In Figure 2, when accessed in the CPU address space (main), the memory (lO) operates as main memory, and when accessed in the CPU address space (frame), the memory (lO) operates as frame memory. Operate.

Therefore, there is no boundary between main memory and frame memory, and there is no need to fix the main memory size and frame memory size. Therefore, the main memory size and frame memory size can be changed as needed, and it is possible to cope with page size fluctuations and frame size fluctuations, which were disadvantages of the conventional technology, and to use memory efficiently.

Effects of the Invention According to the image processing apparatus of the present invention, as described above, all the memories can be used as the main memory and the frame memory, and the sizes of each can be changed.

[Brief explanation of the drawing]

FIG. 1 is an electrical block diagram of an image processing device showing one embodiment of the present invention, FIG. 2 is an explanatory diagram showing the relationship between the CPU address space and memory of the image processing device of FIG. 1, and FIG. 3 is a conventional FIG. 4 is an electrical block diagram of an exemplary image processing apparatus, and is an explanatory diagram showing the relationship between the CPU address space, main memory, and frame memory of the image processing apparatus of FIG. 3. (1) Central processing unit (CPU), (10)
··memory. Patent applicant Konica Corporation @Figure 1 Figure 2

Claims (1)

[Claims] In an image processing device having a main memory for storing program data, received data, page data, etc. and a frame memory for storing bit patterns, the main memory and the frame memory are physically arranged in the same address space. An image processing device characterized by: