JPH0229028A - Output circuit - Google Patents
Output circuitInfo
- Publication number
- JPH0229028A JPH0229028A JP63179401A JP17940188A JPH0229028A JP H0229028 A JPH0229028 A JP H0229028A JP 63179401 A JP63179401 A JP 63179401A JP 17940188 A JP17940188 A JP 17940188A JP H0229028 A JPH0229028 A JP H0229028A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- channel mos
- channel
- mos transistor
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003247 decreasing effect Effects 0.000 abstract 2
- 238000007599 discharging Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 102200076873 rs104894831 Human genes 0.000 description 1
- 102220082323 rs35269563 Human genes 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置の出力端子に接続される出
力回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit connected to an output terminal of a semiconductor integrated circuit device.
従来この種の出力回路は第３図に示すようなインバータ
回路２段を接続したものが用いられていた。すなわち、
各インバータ回路はＰチャンネルＮ１０Ｓトランジスタ
６とＮ４−ヤンネルＭｏＳトランジスタとを電源間で従
属接続１−、ゲートを共通接続１−て入力と１．、ドレ
インを共通接続して出力と１．ていた。前段インバータ
回路の共通ゲートを入力端子１（ＩＣ内の他の回路への
接続点）に接続１７、前段インバータ回路の共通ドレイ
ンを抵抗１０を介して後段インバ・−夕回路の共通ゲー
トに接続し、後段インバータ回路の共通ドレインに出力
端子８を接続していた。。Conventionally, this type of output circuit has been constructed by connecting two stages of inverter circuits as shown in FIG. That is,
Each inverter circuit has a P-channel N10S transistor 6 and an N4-Yannel MoS transistor connected in a dependent manner between the power supply and the gates connected in common to the input and the input. , the drains are connected in common and the output and 1. was. Connect the common gate of the front-stage inverter circuit to the input terminal 1 (connection point to other circuits in the IC) 17, and connect the common drain of the front-stage inverter circuit to the common gate of the rear-stage inverter circuit through the resistor 10. , the output terminal 8 was connected to the common drain of the subsequent inverter circuit. .
−［、述した従来の出力回路は出力付加容量の充放電電
流のピーク値が犬であり、そのため電源グランドの電位
が電源及びグランドインピーダンスのために変動すると
いう欠点があった。- [The conventional output circuit described above has a drawback that the peak value of the charging/discharging current of the output additional capacitor is small, and therefore the potential of the power supply ground fluctuates due to the power supply and ground impedance.
このため第３図に示す様にインバータ回路の入ｆ７に抵
抗１０を付加した回路を使用することが多かった。とこ
ろがこれではインバータ回路の入力電圧の変化（ライズ
タイム、ホールタイム）が太キくなりインバータ回路に
電源からグランドへと貫通電流が流れてしまう新たな欠
点が生じた。For this reason, as shown in FIG. 3, a circuit in which a resistor 10 is added to the input f7 of the inverter circuit is often used. However, this introduced a new drawback: the changes in the input voltage (rise time, hole time) of the inverter circuit became large, and a through current flowed from the power supply to the ground in the inverter circuit.
本発明によれば、入力端子とインバータの入力と第１の
ＰチャンネルＭＯＳトランジスタのゲートと第２ＯＮチ
ヤ／ネルＭＯ８＋−ラソジスタのゲートとを接続し、該
インバータの出力と第３のＭｏ８トランジスタのドレイ
ンと第４のぺ４０Ｓ ｌ’ランジヌタのドしインとを接
続し、該第１ノＰチヤンネルトう”、−二；スタのソー
スと該第３のＭＯＳトランジスタのソースと第５の１ン
チヤ、・ネ、＋ｉ−へ・１０Ｓトランジスタ０ゲートと
を接続し該第２のＮチャンネルＭ ＯＳ ｔ−ランジス
タロ４のＭｏ８）う／・、多スタの′：２−スと第６の
ＮチャンネルＭｏ８＋−ランジスタのゲートとを接続し
、該第１のＰチャ／ネルＭＯ３Ｉ−ランジスタのドレイ
ンと該第５のＰ＋ヤンネルＭｏ８トランジスタのトド・
インとを電源の正電極に接続し、該第５０Ｐチキンネル
ＭＯＳ ） ５ンジスタのソー ヌ、ト該第６のＮチャ
ンネルＭｏ３トランジスタのド１／インとを出力端子に
接続Ｌ、該第２のＮチャンネルＭＯＳトランジスタのソ
ースと該第６のＮチャンネルＭｏ８トランジスタのソー
スとを該電源の負電極に接続し、該第３のＭｏ８トラン
ジスタの導通。According to the present invention, the input terminal, the input of the inverter, the gate of the first P-channel MOS transistor, and the gate of the second ON channel MO8 + - MOS transistor are connected, and the output of the inverter and the drain of the third Mo8 transistor are connected. and the input of the fourth P40S l' terminal, and connect the source of the first P channel, the source of the third MOS transistor, and the fifth first channel. Connect the 0 gate of the 10S transistor to the 0 gate of the second N-channel MOS t-transistor, and and the drain of the first P+channel MO3I- transistor and the gate of the fifth P+channel MO8 transistor.
Connect the input and output terminals of the 50P transistor to the positive electrode of the power supply, and connect the output terminals of the 50P transistor and the input and output terminals of the sixth N-channel Mo3 transistor to the output terminals. The source of the channel MOS transistor and the source of the sixth N-channel Mo8 transistor are connected to the negative electrode of the power supply, and the third Mo8 transistor is turned on.
非導通の状態は該第４のＭｏ８トランジスタの導通、非
導通との状態と反対の関係とし、かつ該第１のＰ＋ヤン
ネルＭｏ８トランジスタの導通、非導通の状態は該第３
のＭｏ８トランジスタの導通、非導通との状態と反対の
関係とする出力回路を得る。The non-conducting state is opposite to the conducting/non-conducting state of the fourth Mo8 transistor, and the conducting/non-conducting state of the first P+ channel Mo8 transistor is opposite to the conducting/non-conducting state of the fourth Mo8 transistor.
An output circuit is obtained in which the conduction and non-conduction states of the Mo8 transistor are reversed.
本発明の出力回路は出力負荷充放電時の電源。The output circuit of the present invention is a power source for charging and discharging an output load.
グランド電位の変動が少なく、出力回路自身の貫通電流
が少ないという効果を有する。This has the effect that there is little variation in the ground potential and that the through current of the output circuit itself is small.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第一の実施例である。図中２．５．７
はＮチャンネルＭｏ３トランジスタ、３．４．６はＰチ
ャンネルＭＯＳトランジスタ、９はインバータである。FIG. 1 shows a first embodiment of the invention. 2.5.7 in the figure
is an N-channel Mo3 transistor, 3.4.6 is a P-channel MOS transistor, and 9 is an inverter.
今入力端子の電位が低レベルから高レベル（ＯＶからＶ
ＤＤ電位）と変わった直後を考えると、ＰチャンネルＭ
ｏｓ＋・ランジスタ３はＯＮからＯＦＦに変り、Ｎチャ
ンネルＭｏ８トランジスタ５はＯＦＦからＯＮとなる。The potential of the input terminal is now from low level to high level (OV to V
DD potential), P channel M
The os+ transistor 3 changes from ON to OFF, and the N-channel Mo8 transistor 5 changes from OFF to ON.
その後インバータ９の出力抵抗とＮチャンネルＭＯＳト
ランジスタ２のオン抵抗とでゆっくりとＰ＋ヤンネルＭ
ｏ８トランジスタロのゲート電圧を下げることになる。After that, the output resistance of the inverter 9 and the on-resistance of the N-channel MOS transistor 2 slowly increase the P+Yannel M.
This will lower the gate voltage of the o8 transistor.
従ってまず始めにＮチャンネルトランジスタ７がＯＦＦ
となり次にゆっくりとＰチャンネルトランジスタ６がＯ
Ｎとなる９ このためＰチャンネルとＮチャンネルの２
つのトランジスタ６と７とが同時にＯＮとなって電源か
らグランドへ貫通電流が流れることがない。またＰチャ
ンネルトランジスタ６のゲート電圧がゆっくり下がるた
め出力端子８の電位の動きもゆっくりである。このため
電源グランドインピーダンスのための電源グランド電位
の変動も少ない７入力端子の電圧が高レベルから低レベ
ル（ｖＤＤ電位からＯＶ）へと変わった場合は以上の説
明でＰチャンネルとＮチャンネルのトランジスタ６と７
とをＭｏ８＋−ランジスタ４、Ｐチャンネルトランジス
タ３をＮチャンネルトランジスタ５、Ｐチャンネルトラ
ンジスタ６をＮチャンネルトランジスタ７と読み替えた
動作となる。Therefore, first of all, N-channel transistor 7 is turned off.
Then, the P-channel transistor 6 slowly turns to O.
9 becomes N. Therefore, 2 of P channel and N channel
Two transistors 6 and 7 are turned ON at the same time, and no through current flows from the power supply to the ground. Furthermore, since the gate voltage of the P-channel transistor 6 falls slowly, the potential at the output terminal 8 also moves slowly. Therefore, there is little variation in the power supply ground potential due to the power supply ground impedance.7 When the voltage at the input terminal changes from a high level to a low level (vDD potential to OV), the P-channel and N-channel transistors 6 and 7
The operation is as follows: Mo8+- transistor 4, P-channel transistor 3 as N-channel transistor 5, and P-channel transistor 6 as N-channel transistor 7.
第２図は本発明の第二の実施例の出力回路である。第一
の実施例に対？、ＭＯＳトランジスタ２′をＰチャンネ
ルＭＯ８）ランシスタで実現し、ＭＯＳトランジスタ４
′をＮチャンネルで実施したものである。回路動作と１
．では第一の実施例と同じである。FIG. 2 shows an output circuit of a second embodiment of the present invention. Contrary to the first embodiment? , MOS transistor 2' is realized by a P-channel MO8) transistor, and MOS transistor 4
' is implemented on N channels. Circuit operation and 1
．． This is the same as the first embodiment.
以上説明した様に、本発明は出力負荷充放電時の電源グ
ランド電位の変動が少なく、出力回路自身の電源からグ
ランドへの貫通電流が少ないという利点があり、半導体
集積回路に用いれば電源グランドのレイアウトを余り気
にすることもなく低消費電力であるという効果がある。As explained above, the present invention has the advantage that there is little fluctuation in the power ground potential during charging and discharging of the output load, and that there is little through current from the power supply of the output circuit itself to the ground. This has the effect of low power consumption without having to worry too much about the layout.
３図は従来例を示す回路図である。FIG. 3 is a circuit diagram showing a conventional example.
１・・・・・・入力端子、２，４．２’ ４’・・・
・・・ＭＯＳトランジスタ、３，６・・・・・・Ｐチャ
ンネルＭＯＳトランジスタ、５，７・・・・・・Ｎチャ
ンネルＭＯＳトランジスタ、８・・・・・・出力端子、
９・・・・・・インバータ、１０・・・・・・抵抗。1... Input terminal, 2, 4.2'4'...
...MOS transistor, 3,6...P channel MOS transistor, 5,7...N channel MOS transistor, 8...output terminal,
9... Inverter, 10... Resistor.
代理人 弁理士 内 原 晋Agent: Patent Attorney Susumu Uchihara
Claims (1)
ＯＳトランジスタのゲートと第２のＮチャンネルＭＯＳ
トランジスタのゲートとを共通に接続し、該インバータ
の出力部と第３のＭＯＳトランジスタのドレインと第４
のＭＯＳトランジスタのドレインとを共通に接続し、該
第１のＰチャンネルトランジスタのソースと該第３のＭ
ＯＳトランジスタのソースと第５のＰチャンネルＭＯＳ
トランジスタのゲートとを共通に接続し、該第２のＮチ
ャンネルＭＯＳトランジスタのドレインと該第４のＭＯ
Ｓトランジスタのソースと第６のＮチャンネルＭＯＳト
ランジスタのゲートとを共通に接続し、該第１のＰチャ
ンネルＭＯＳトランジスタのドレインと該第５のＰチャ
ンネルＭＯＳトランジスタのドレインとを電源の正電極
に接続し、該第５のＰチャンネルＭＯＳトランジスタの
ソースと該第６のＮチャンネルＭＯＳトランジスタのド
レインとを出力端子に接続し、該第２のＮチャンネルＭ
ＯＳトランジスタのソースと該第６のＮチャンネルＭＯ
Ｓトランジスタのソースとを該電源の負電極に接続し、
該第３のＭＯＳトランジスタの導通、非導通の状態は該
第４のＭＯＳトランジスタの導通、非導通との状態と反
対の関係とし、かつ該第１のＰチャンネルＭＯＳトラン
ジスタの導通、非導通の状態は該第３のＭＯＳトランジ
スタの導通、非導通との状態と反対の関係とすることを
特徴とする出力回路Input terminal, input part of inverter and first P channel M
Gate of OS transistor and second N-channel MOS
The gates of the transistors are commonly connected, and the output part of the inverter, the drain of the third MOS transistor, and the fourth
The drains of the first P-channel transistors are commonly connected, and the source of the first P-channel transistor and the third MMOS transistor are connected in common.
Source of OS transistor and fifth P-channel MOS
The gates of the transistors are commonly connected, and the drains of the second N-channel MOS transistor and the fourth MOSFET are connected in common.
The source of the S transistor and the gate of the sixth N-channel MOS transistor are connected in common, and the drain of the first P-channel MOS transistor and the drain of the fifth P-channel MOS transistor are connected to the positive electrode of the power supply. The source of the fifth P-channel MOS transistor and the drain of the sixth N-channel MOS transistor are connected to the output terminal, and the second N-channel MOS transistor
The source of the OS transistor and the sixth N-channel MO
Connecting the source of the S transistor to the negative electrode of the power supply,
The conducting/non-conducting state of the third MOS transistor is opposite to the conducting/non-conducting state of the fourth MOS transistor, and the conducting/non-conducting state of the first P-channel MOS transistor. is an output circuit characterized in that has an opposite relationship to the conduction and non-conduction states of the third MOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63179401A JP2541289B2 (en) | 1988-07-18 | 1988-07-18 | Output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63179401A JP2541289B2 (en) | 1988-07-18 | 1988-07-18 | Output circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0229028A true JPH0229028A (en) | 1990-01-31 |
| JP2541289B2 JP2541289B2 (en) | 1996-10-09 |
Family
ID=16065222
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63179401A Expired - Lifetime JP2541289B2 (en) | 1988-07-18 | 1988-07-18 | Output circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2541289B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10179301B2 (en) | 2014-07-24 | 2019-01-15 | Huber Se | Elongated scraper profile |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56103536A (en) * | 1980-01-23 | 1981-08-18 | Hitachi Ltd | Mis output circuit |
-
1988
- 1988-07-18 JP JP63179401A patent/JP2541289B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56103536A (en) * | 1980-01-23 | 1981-08-18 | Hitachi Ltd | Mis output circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10179301B2 (en) | 2014-07-24 | 2019-01-15 | Huber Se | Elongated scraper profile |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2541289B2 (en) | 1996-10-09 |
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