JPH02290377A - Picture processor - Google Patents

Abstract

PURPOSE:To avoid displeasure of a visual sense at changeover by reading sequentially a preceding picture signal by one pattern stored in a storage means from the point of time of the changeover of the kind of a picture signal, decreasing gradually the level and outputting the signal and outputting the picture signal to be read succeedingly while being increased gradually. CONSTITUTION:After a picture signal recorded on a magnetic tape 11 is read by a magnetic head 14, the signal is demodulated by an FM demodulation circuit 16 and a de-emphasized analog picture signal is converted into a digital picture signal 18 and fed to a 1st multiplication circuit 19 and a picture memory 20. When a picture switching signal is detected, the level of the preceding picture signal by one pattern stored in the 1st multiplication circuit 19 and the memory 20 is gradually decreased and the level of the picture signal to be read succeedingly is gradually increased by a 2nd multiplication circuit 21 simultaneously. Thus, the change in the picture when different kinds of the picture signal is switchingly reproduced is relaxed and the displeasure on a visual sense is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus that performs image processing when reproducing images from a recording medium.

[Prior Art] For example, when reproducing an image signal from a recording medium such as a magnetic tape, recorded magnetic information is read out continuously,
This is demodulated to become a video signal and output as is. Therefore, when two different types of image signals are consecutively recorded on a recording medium, one image signal is successively read out, followed by the other image signal.

[Problems to be Solved by the Invention] According to the image reproducing device as described above, when two different types of image signals are successively reproduced, at the time of switching between them,
This is visually very undesirable because the screen suddenly changes from one image signal to the other image signal.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an image processing apparatus that does not cause visual unsightliness when switching between two image signals when reproducing different types of image signals that are continuously recorded.

[Means for Solving the Problems] A feature of the present invention that achieves the above-mentioned object is an image processing device that processes image signals read from a recording medium on which different types of image signals are recorded, 1 one after another until the type of image signal is switched.
storage means for storing the image signal corresponding to a screen; reduction means for gradually decreasing the level of the image signal read from the storage means from the above-mentioned switching point; The present invention includes an increasing means for gradually increasing the level from the above-mentioned switching point, and an adding means for adding the decreased level of the image signal and the increased level of the image signal.

[Operation] From the point in time when the type of image signal is switched, the previous one screen worth of image signals stored in the storage means are sequentially read out, their levels are gradually decreased, and the signals are sequentially output. At the same time, the levels of the image signals that are successively read from the recording medium are gradually increased and sequentially output. By synchronously adding the levels of both image signals output sequentially, the switching of the image signals becomes smooth, and the unsightly appearance at the time of switching is eliminated.

[Example code] Embodiments of the present invention will be described in detail below using the drawings.

FIG. 1 shows a VT as an embodiment of the image processing device of the present invention.
1 schematically represents the electrical configuration of R (video tape recorder).

In the figure, numeral 10 indicates a pre-emphasis circuit to which a video signal (image signal) is supplied from the outside via an input terminal I1, and numeral 12 indicates an FM (frequency modulation) modulation circuit connected to the pre-emphasis circuit 10. There is. An image signal recording amplifier 1 is provided on the output side of this FM modulation circuit 12.
A magnetic head 14 for image signals is connected via 3.

The magnetic head 14 further includes an image signal head amplifier 15.
An FM demodulation circuit 16 is connected via the FM demodulation circuit 16.

A de-emphasis circuit 1 is provided on the output side of the FM demodulation circuit 16.
7 via A/D (Analog/Digital) converter 18
is connected. A first multiplication circuit 19 and an image memory 20, which correspond to the increasing means of the present invention, are connected to the output side of the A/D converter I8.

The image memory 20 corresponds to the storage means of the present invention, and the second multiplication circuit 21, which corresponds to the reduction means of the present invention, is connected to its output side. An adder 22 is connected to the output sides of the first multiplication circuit 19 and the second multiplication circuit 2I, and a D/A (digital/analog) converter 23 is connected to the output sides thereof. The output side of the D/A converter 23 is connected to an output terminal 24.
The image signal is output to the outside via.

Image memory 20, first multiplication circuit 19 and second multiplication circuit 2
I is connected to a microcomputer 25, and performs image processing, which will be described later, in response to instructions from the microcomputer 25. The microcomputer 25 further includes an image switching timing signal generation circuit 26 composed of, for example, a monostable multivibrator, and an image switching timing signal detection circuit 27 composed of, for example, a comparator.
are connected.

A magnetic head 30 for control signals is connected to the signal generation circuit 26 and signal detection circuit 27 via a control signal recording amplifier 28 and a control signal head amplifier 29, respectively.

The magnetic head 14 is configured to record information on the video track of the magnetic tape 31, and the magnetic head 30 is configured to record information on the control track of the magnetic tape 31. This magnetic tape 3l corresponds to the recording medium of the present invention.

The image signal applied from the outside via the input terminal 11 is
After being pre-emphasized by the pre-emphasis circuit IO, the signal is FM-modulated by the FM modulation circuit 12.

The modulated signal is amplified by the recording amplifier 13 and then recorded on the video track of the magnetic tape 3l via the magnetic head l4.

A magnetic head 30 simultaneously sends an image signal to the magnetic tape 31.
A control signal is recorded via. In this embodiment, this control signal includes an image switching timing signal. The image switching timing signal represents switching retiming of different types of image signals. If images that are completely different from the current image are to be recorded continuously, the operator instructs the microcomputer 25 to that effect using a key. As a result, the microcomputer 25 operates the signal generation circuit 26, and as a result,
The image switching timing signal is recorded on the control track of the magnetic tape 31 as part of the control signal.

On the other hand, this control signal recorded on the control track of the magnetic tape 31 is read out by the magnetic head 30 and then applied to the signal detection circuit 27 via the head amplifier 29. Thereby, the image switching timing signal can be detected and a TTL level digital signal can be obtained. When the image switching timing signal is applied from the signal detection circuit 27, the microcomputer 25 transmits a load signal as shown in FIG. 2 to the image memory 20 and the first multiplication circuit 1.
9 and the second multiplication circuit 2l.

The image signal recorded on the video track of the magnetic tape 31 is read out by the magnetic head 14, demodulated by the FM demodulation circuit 16, and de-emphasized by the de-emphasis circuit 17. The de-emphasized analog image signal is converted into a digital image signal by an A/D converter 18, and then transferred to a first multiplication circuit 19 and an image memory 2.
0.

The image memory 20 is a frame memory and has a capacity to store image signals for one screen. This image memory 20 always stores the latest A/D converted image signal for one frame unless the word signal becomes 1 when an image switching timing signal is detected.

The image switching timing signal is detected and the load signal becomes 1.
Then, while this load signal is 1, the image memory 20 retains the contents stored before the image switching timing signal was detected. Also, during this time, an image signal is read out from the image memory 20 and applied to the second multiplier circuit 2l.

The first multiplication circuit 19 multiplies the value of the image signal applied from the A/D converter 18 by a multiplier value α shown in FIG. As shown in the figure, the multiplier value α is equal to 1 until the image switching timing signal is detected and the load signal becomes 1, and after the image switching timing signal is detected, the multiplier value α becomes 0.
While the load signal is 1, it gradually increases from 0 to 1.

The second multiplier circuit 2l multiplies the value of the image signal applied from the image memory 20 by a multiplier value β shown in FIG. As shown in the figure, the multiplier value β is equal to 0 until the image switching timing signal is detected and the load signal becomes 1. gradually decreases from 1 to 0 while it is 1.

The image signal output from the first multiplication circuit 19 and the image signal output from the second multiplication circuit 2l are applied to the adder 22 and added together. The output of the adder 22 is applied to a D/A converter 23, converted into an analog image signal, and then outputted to the outside via an output terminal 24.

Therefore, according to the apparatus of this embodiment, as shown in FIG.
When the image switching timing signal is detected, the level of the image signal before switching gradually decreases, and at the same time, the level of the image signal after switching gradually increases.

Next, the configuration and operation of the first and second multiplier circuit portions described above will be explained in more detail. Figure 4 shows the first and second
This shows the multiplication circuit part in more detail.

In the same figure, +91, 19b s 19c and 19
d is a latch connected to the output of A/D converter l8, 1
9e each indicates an up counter. These latches 19g, 19b, 19c and 19d and the up counter 19e constitute the first multiplier circuit 19 in FIG.

Each bit output Qll, Qlb of the up counter 19e
, Qle and Qld are latches 19i, 19b s
It is connected to the clear input CLEAR of 19c and 19d, respectively.

The outputs of the latches 19@, 19b s 19c and 19d are connected in parallel to the input of the adder 22. Each latch 19! , L9b S19c and 19d output the latched contents when the clear input CLEAR is 1, and output 0 regardless of the latched contents when the clear input CLEAR is 0. The latch 19a latches the input multiplied by 1/l6, and the latch 19b latches the input by 1/l6.
The latch 19c is configured to latch the content multiplied by 11, the latch 19c latches the content multiplied by 1/4 with respect to the input, and the latch 19d is configured to latch the content multiplied by 172 with respect to the input. Such a multiple of each latch is determined by the A/D converter l8
This can be realized by connecting each bit output of each latch to the bit input of each latch as shown in FIG.

Furthermore, in FIG. 4, 21a s 21b s 21
C and 21d are latches connected to the output of the image memory 20, and 21e is a down counter, respectively.

These latches 21a, 2lb, 21c and 2
1d and the down counter 21e constitute the second multiplier circuit 21 in FIG. down counter 21
Each bit output Q2i s Q2b s Q2c and Q2d of e is connected to the clear input CLEAR of the latches 21a, 21b s 21c and 21d, respectively. The outputs of the latches 21i, 21b, s21c and 21d are connected in parallel to the input of the adder 22. Other configurations and functions of the latches 21a s 21b s 21c and 21d are as described above for the latches 19i and 19b.
s Exactly the same as in 19c and 19d.

As shown in FIG. 6, the microcomputer 25 raises the load signal to 1 in synchronization with the rise of the image switching timing signal applied by the signal detection circuit 27, and the clock is counted up to a predetermined set value. This value is held at 1 until the set value is exceeded, and the value is reduced to 0. In this embodiment, this set value is 16, as shown in FIG.

When the load signal applied from the microcomputer 25 is 1, the up counter 19e and the down counter 2
1e counts the clocks. Therefore, each bit output of these counters Qta s qlb %Qlc N
Qlds Q2! , Q2b s Q2c and Q2
d changes as shown in FIG.

Note that the up counter 19e and the down counter 21e
is set to the initial value when the load signal is 0. 6th
As shown in the figure, in the initial state, the up counter 19e outputs each bit Qla, Qlb, Ql
c and Qld are all 1, and the down counter 2b has each bit output Q2a, Q2b, Q2c in the initial state.
and Q2d are all 0.

When the load signal is 0, all outputs of the up counter 19e are 1, so all latches 19i, 19b,
19c and 19d continuously output their contents. On the other hand, since all of the outputs of the down counter 21e become 0, the outputs of all the latches 21a%2lb, 21c, and 21d become 0. Therefore, in this case, the image signal applied from the A/D converter 18 is multiplied by a multiplier maintained at a constant value, and then D/A converted and output to the outside.

When the load signal becomes 1, the up counter 19e counts up the clock and generates bit outputs Qll % Qlb, old C and Qld as shown in FIG.

Such outputs Qli, Qlb s Qlc and Ql
Each latch 19 by d! , 19b S19c and 1
Since 9d is driven, the multiplier increases gradually from 0 to 1 in a stepwise manner. The image signal applied from the A/D converter 18 is multiplied by this multiplier and applied to the adder 22. On the other hand, the down counter 21e counts down the clock and outputs bits Q21, Q2 as shown in FIG.
b % Generate Q2c and Q2d. Since the latches 21i s 21b 121c and 21d are driven by the outputs Q2i, Q2b s Q2e and Q2d, the multiplier gradually decreases from 1 to 0 in a stepwise manner.

The image signal applied from the image memory 2G is multiplied by this multiplier and applied to the adder 22. That is, in this case, the first
Multiplier value α of multiplier circuit l9 and multiplier value β of second multiplier circuit 21
changes as shown in FIG.

As a result, as shown in Figure 3, the level of the image signal before switching gradually decreases, and at the same time, the level of the image signal after switching gradually increases, so when different types of image signals are reproduced. , the image changes gradually when both image signals are switched, and no visual unsightliness occurs.

Although the embodiment of the VTR has been described above, the image processing device of the present invention can be applied to various devices capable of recording images digitally, such as a DAT (digital audio tape recorder) and a video disc recorder. can.

In the case of a video disk recorder, an optical disk, a magneto-optical disk, or a magnetic disk is used as a medium for recording image signals, as shown in FIG. In the same figure,
32 is a disk, 33 is a motor for driving the disk 32,
Reference numeral 34 indicates a pickup.

[Effects of the Invention] As explained in detail above, according to the present invention, image signals read from a recording medium on which different types of image signals are recorded are sequentially displayed one screen at a time until the type of image signal is switched. storage means for storing the level of the image signal read from the storage means gradually from the above-mentioned switching point; Since the image signal is continuously recorded, the image signal is continuously recorded. When different types of image signals are reproduced, no visual discomfort occurs when switching between the two image signals.

[Brief explanation of drawings]

FIG. 1 is a block diagram schematically showing the electrical configuration of a video tape recorder as an embodiment of the image processing device of the present invention, FIG. 2 is a signal waveform diagram of each part in the embodiment of FIG. 1, and FIG. 4 is a block diagram showing in more detail the configuration of the first and second multiplier circuit portions in the embodiment of FIG. 1. 5 is a block diagram showing a part of the electrical configuration in FIG. 4 in more detail, FIG. 6 is a signal waveform diagram of each part in the configuration example of FIG. 4, and FIG. FIG. 2 is a configuration diagram schematically showing a part of an embodiment of the present invention. 10...Briemphasis circuit, ll...
...Input terminal, l2...FM modulation circuit, 13.
... Image signal recording amplifier, 14 ... Magnetic head, l5 ... Image signal head amplifier, 16
...FM demodulation circuit, 17... De-emphasis circuit, l8... A/D converter, 19.
...First multiplication circuit, 19a s 19b s 1
9c % 19d s 21a, 2lb, 21
c % 21d...Latch, 19e...
・Up counter, 20... Image memory, 2l
...Second multiplication circuit, 21e... Down counter, 22... Adder, 23...
D/A converter, 24... Output terminal, 25...
... Microcomputer, 26 ... Image switching timing signal generation circuit, 27 ... Image switching timing signal detection circuit, 28 ... Control signal recording amplifier, 29 ... ... Control signal head amplifier, 30 ... Magnetic head, 31
······Magnetic tape. Figure 3 Enemies, (504) Sharp Corporation

Claims (1)

[Claims] An image processing device that processes image signals read from a recording medium on which different types of image signals are recorded, the image processing device processing the image signals from the recording medium for one screen one after another until the type of image signal is switched. storage means for storing the level of the image signal read from the storage means; reducing means for gradually reducing the level of the image signal read from the storage means from the switching point; and a reduction means for gradually decreasing the level of the image signal read from the recording medium subsequent to the stored image signal. An image processing apparatus comprising: an increasing means for gradually increasing the level from the switching point; and an adding means for adding the decreased level of the image signal and the increased level of the image signal.