JPH02292833A - Ldd transistor - Google Patents

Abstract

PURPOSE:To reduce the asymmetry of source and drain by oblique ion- implantation process by a method wherein the whole gate electrode is composed of a gate layer and sidewall gate layers provided on both sides of the gate layer so that low concentration impurity diffused layers may be formed underneath the sidewall gate layers. CONSTITUTION:The title LDD transistor is composed of a gate electrode 12 comprising a gate layer 12a and sidewall gate layers 12b provided on both sides of the gate layer 12a as well as low concentration impurity diffused layers 13 formed underneath the sidewall gate layers 12b. For example, a silicon oxide film 11 is formed on the surface of a silicon substrate 10 and then the gate layer 12a comprising polycrystalline silicon is formed on the silicon oxide film 11. Next, arsenic is obliquely ion-implanted to form the low concentration impurity diffused layers (n<-->) 131, 132. Next, after forming the sidewall layers 12b1, 12b2 on both sides of the gate layer 12a, the arsenic is also obliquely ion- implanted to form the other low concentration impurity diffused layers (n<->) 141, 142. Finally, after forming spacers 151, 152 comprising silicon oxide on both sides of the gate electrode 12, the arsenic is repeatedly ion-implanted to form high concentration impurity diffused layers (n<->)161, 162.

Description

Detailed description of the invention (lltl required) So-called LDD (
In order to reduce source/drain asymmetry caused by diagonal ion implantation, sidewall gate layers are provided on both sides of the gate layer, and the gate electrodes are separated at intervals, and the sidewall gate layers are The structure is such that a low concentration impurity diffusion layer is formed underneath.

(Industrial Application Field) The present invention relates to a so-called LDD transistor having a low tide impurity diffusion region as part of the source and drain for relaxing the i!a electric field.

In recent years, there has been a demand for miniaturization of transistors used in LSIs, and this trend is expected to become even stronger in the future. Such miniaturization causes problems such as fluctuations in threshold voltage TH and mutual conductance due to hot electrons, and therefore it is necessary to suppress the hot electron effect. Therefore, LDD transistors that have low concentration impurity diffusion regions as part of the source and drain to alleviate the high electric field caused by these hot electrons have come to be used.

(Prior art) A general LDD transistor generally has a gate electrode of polycrystalline silicon on an oxide film on the surface of a substrate, and a low concentration impurity diffusion layer (n-) which is part of the source and drain by ion implantation. Next, a substrate such as silicon oxide is provided on both sides of the gate electrode, and the source and drain, which are high concentration impurity diffusion layers (n+), are formed by ion implantation.In this case, a low 81 degree impurity diffusion layer (n+) is formed. 1) acts as a region for relaxing high electric fields, and in the LDD structure, optimization of the impurity concentration of this n″′ layer is important.

[Problem to be solved by the invention]

In conventional DD transistors, ions are implanted obliquely into the wafer to prevent channeling.
and formed an n+ layer. For example, as shown in FIG. 3, a polycrystalline silicon gate electrode 3 having a thickness of 0.5 μl to 0.7 μm and a width of about 1 μl is provided on a silicon oxide film 2 on the surface of a silicon substrate 1, and ions are obliquely implanted. Next, silicon oxide substrates 5 are provided on both sides of the gate electrode 3, and ions are obliquely implanted to form a high concentration impurity diffusion layer (n''). ) form 6.

Thus, the conventional LDD transistor is n-IW4
．． Since diagonal ion implantation is performed when forming the n+ layer 6, a negative part may be formed on one side of the gate electrode depending on the wafer mounting position of the ion implanter. The influence of the shaded part (on the right side in FIG. 3) is large, and this becomes an offset part, causing source-drain asymmetry.

An object of the present invention is to provide an LDD transistor that can reduce source-drain asymmetry caused by oblique ion implantation.

[Means to solve the problem]

FIG. 1 shows a diagram of the principle of the present invention. In the figure, 12a is a gate layer, 12b is a sidewall gate layer provided on both sides of the gate layer 12a, and the gate layer 12a and sidewall gate WJ12b constitute a gate electrode. A low concentration impurity diffusion layer 13 is formed under the sidewall gate layer 12b.

[Effect]

When forming the impurity diffusion layer, since ions are implanted obliquely into the wafer to prevent channeling, the low concentration impurity diffusion layer 13 is not formed in the shadow area of the gate layer 12a (the right side in FIG. 1). Therefore, in the present invention, by forming sidewall gate layers 12b on both sides of the gate layer 12a, the gate electrode 1 is made wider than the original gate Il12a.
2, thereby eliminating the offset portion between the gate electrode 12 and the low concentration impurity diffusion H13 on the negative side (right side in the figure). Therefore, source/drain asymmetry caused by oblique ion implantation can be reduced.

〔Example〕

FIG. 2 shows a manufacturing process diagram of an embodiment of the LDD t-transistor according to the present invention. 43 in the same figure (A), a silicon oxide film 11 is formed on the surface of a silicon substrate 10, and a gate layer 12a of polycrystalline silicon is formed on it to a thickness of, for example, 0.5 μm.
It is formed with a width of 0.5 μm to 0.7 μm. Here, for example, using an impurity of arsenic, for example, 80k (!V
Oblique ion implantation of approximately 2×10 12 doses was performed with an energy of
+, 132 is formed. In this case, since oblique ion implantation is performed, depending on the mounting position of the wafer, the low-density impurity diffusion layer (n 2 ) 132 is not formed in the shadow portion on the right side of the gate layer 12a as shown in the figure.

Next, as shown in FIG. 4B, sidewall gate layers 12b1 and 12b each having a width of about 0.3 μm are formed on both sides of the gate layer 42a.
form 2. Gate Il12a and sidewall gate layer 12
The gate electrode 12 is configured in b1.12b2. In this case, the left side n”' − which is not affected by oblique ion implantation
A sidewall gate 12,1 is formed on the Wt 1 3 +, while a sidewall gate 12b2 is formed to a small extent on the right n- layer 132, which is affected by the oblique ion implantation. will be done. Here, for example, using an impurity of arsenic, for example, 1
Perform oblique ion implantation with a culmability of
form. In this case as well, since oblique ion implantation is performed, the low depth impurity diffusion layer (n-) 142 is not formed in the right shadow portion of the right side wall groove 1-12b2.

Next, as shown in the same figure (C), silicon oxide substrates 151 and 152 are formed on both sides of the gate electrode 12. Here, using an impurity such as arsenic, for example, oblique ion implantation is performed at an energy level of 80 kcV with a trace of 4 x 10" doses to form a highly polished impurity diffusion layer (n") 161.1.
62 is formed. After this, the process of forming contact holes, metal wiring, passivation, etc. is the same as the normal process.

In particular, the present invention provides side walls on both sides of the gate layer 12a. route
V12. 12b■ is provided, and the b1 low concentration impurity diffusion layer (n-"-) 13+, 132 is provided below this, so even if oblique ion implantation is performed and there is a negative part, there will be no offset or part. That is, as is clear from FIG. 2(B), n is not formed in the width direction.
The n-1 layer 132 is interposed between the "'' layer 142 and the sidewall gate layer 12b2, thereby making it possible to reduce the source/drain asymmetry compared to the conventional example shown in FIG.

Note that the n− layer is not provided, and the n− layer is not provided from the stage of the gate layer 12a.
It is possible to eliminate the offset portion by forming one layer and then forming the sidewall gate layer, but if you shift it in this way, the sidewall gate layer will exist on the n-layer on the left, for example, where there is no shaded area. In other words, since the electrodes 1 to 1 are present on the low layer, which has a relatively high resistance (it is desirable that nm is under the surface layer), this is undesirable because it causes source/drain asymmetry. . In the present invention, since the extremely low concentration impurity diffusion layer (n--) 13+ is located under the sidewall gate layer 12b1, the above-mentioned disadvantages do not occur.

〔Effect of the invention〕

As explained above, according to the present invention, since the sidewall gate layer is provided on both sides of the gate layer and the low permeability impurity diffusion layer is provided under the sidewall gate layer 1, the shadows generated by oblique ion implantation are The offset portion between the gate electrode and the lightly doped impurity diffusion layer on the partial side can be eliminated, and source/drain asymmetry caused by oblique ion implantation can be reduced.

12 is a gate electrode, 12a is a gate layer, 1 2b . 1 2, 1, 1 2, 2 is the sidewall gate 'i5, 13.13+, 132 is the low concentration impurity diffusion layer (n-"">, 14+, 142 is the low a degree impurity diffusion layer (n-), 15
1.152 is subbase, 1 t3+, 1 62 QlFJ degree impurity diffusion layer (ni is shown).

Patent applicant: Tomitsu Co., Ltd.

[Brief explanation of drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a manufacturing process diagram of an embodiment of the present invention, and FIG. 3 is a structural diagram of a conventional DD transistor. In the figure, 10 is a silicon substrate;

Claims (1)

[Claims] Sidewall gate layers (12b) on both sides of the gate layer (12a).
is provided, and the whole serves as a gate electrode (12), and a low concentration impurity diffusion layer (12b) is provided below the sidewall gate layer (12b).
13) is formed.