JPH02201922A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02201922A
JPH02201922A JP2171289A JP2171289A JPH02201922A JP H02201922 A JPH02201922 A JP H02201922A JP 2171289 A JP2171289 A JP 2171289A JP 2171289 A JP2171289 A JP 2171289A JP H02201922 A JPH02201922 A JP H02201922A
Authority
JP
Japan
Prior art keywords
region
transistor
semiconductor device
ion implantation
different
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2171289A
Other languages
Japanese (ja)
Inventor
Takao Yasue
孝夫 安江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2171289A priority Critical patent/JPH02201922A/en
Publication of JPH02201922A publication Critical patent/JPH02201922A/en
Pending legal-status Critical Current

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、FIBを用いて半導体基板に作成したトラ
ンジスタネ純物領域の深さを変化させ、局所的な領域に
異なる性質のトランジスタを形成し、その特性を評価す
る技術に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] This invention changes the depth of a transistor pure region created in a semiconductor substrate using FIB to form transistors with different properties in local regions. It relates to technology for evaluating the characteristics of

〔従来の技術〕[Conventional technology]

第2図(IL)〜(6)は従来の半導体装置の製造方法
を工程を追って示す断面側面図である。図において(1
]は半導体基板結晶、(2)はトランジスタ分離領域、
(3)はトランジスタゲート電極、(4)はレジスト、
口。
FIGS. 2(IL) to 2(6) are cross-sectional side views showing step by step a conventional method for manufacturing a semiconductor device. In the figure (1
] is a semiconductor substrate crystal, (2) is a transistor isolation region,
(3) is a transistor gate electrode, (4) is a resist,
mouth.

鰻はトランジスタ形成のため不純物のイオン注入を示し
、ell、圃はイオン注入l511.@によって形成さ
れた不純物注入領域を示す。なお、イオン注入らυとイ
オン注入@z1及び不純物領域間と不純物領域(財)は
それぞれ異なるエネルギーのイオン注入、異なる深さの
不純物領域を示している。
The eel uses impurity ion implantation to form a transistor, and the ell and field use ion implantation l511. An impurity implantation region formed by @ is shown. Note that ion implantation υ and ion implantation @z1, between impurity regions, and impurity region (material) indicate ion implantation with different energies and impurity regions with different depths, respectively.

次に製造方法について説明する。一つの半導体基板上に
異なる下ランジスタを形成しようとする場合、まず半導
体基板結晶(1)にトランジスタ分離領域(2)を酸化
膜などで形成し、それ以外の活性領域上にトランジスタ
ゲート電極(3)を設ける。例えば異なる2つのトラン
ジスタを形成する場合には、第2図(&)のように一方
のトランジスタ領域を、レジスト(罰でカバーリングし
、全面にイオン注入団を行う。するとレジスト(4)で
覆われていないトランジスタゲート電極(3)の端には
、不純物注入領域−が形成される。次に第2図(息)で
レジスト(4)で覆った領域のレジスト(4)を除去し
、もう一方のトランジスタ領域をレジスト(4)でカバ
ーリングして、第2図(b)に示すごとく異なるエネル
ギーのイオン注入口を行う。これらのレジスト(4)の
操作により、第2図(6)に示すごとくイオン注入深さ
の異なるトランジスタを一つのウェハ内に作成すること
ができる。なお、更に多くの異なるトランジスタを形成
したい場合には、上記のプロセスを繰り返すことになる
Next, the manufacturing method will be explained. When trying to form different lower transistors on one semiconductor substrate, first, a transistor isolation region (2) is formed on the semiconductor substrate crystal (1) using an oxide film, etc., and a transistor gate electrode (3) is formed on the other active region. ) will be established. For example, when forming two different transistors, as shown in FIG. An impurity implantation region is formed at the end of the transistor gate electrode (3) that is not covered.Next, the resist (4) in the region covered with the resist (4) is removed as shown in FIG. One transistor region is covered with a resist (4), and ion implantations with different energies are performed as shown in Figure 2(b).By manipulating these resists (4), the area shown in Figure 2(6) is formed. As shown, transistors with different ion implantation depths can be fabricated in one wafer. Note that if more different transistors are desired to be formed, the above process will be repeated.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体装置の製造方法は以上のようになされるた
め、製造プロセス工程が複雑になり、かつ増大する問題
点があった。
Since the conventional method for manufacturing a semiconductor device is performed as described above, the manufacturing process becomes complicated and the problem increases.

この発明は上記のような問題点を解消するためになされ
たもので、製造プロセス工程を減らし、比較的簡便に一
つの基板上に異なるトランジスタを形成することができ
る。
This invention was made to solve the above-mentioned problems, and it is possible to reduce the number of manufacturing process steps and form different transistors on one substrate relatively easily.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置の製造方法は、FIBの持つ
局所加工性を利用したもので、簡便にトランジスタ特性
の変化が可能である・ 〔作用〕 この発明における半導体装置の製造方法は、FIBを用
いてトランジスタ活性領域を局所的にプリアモルファス
化し、その後、全体にイオン注入を行う。
The method for manufacturing a semiconductor device according to the present invention utilizes the local processability of FIB, and can easily change transistor characteristics. The transistor active region is locally made pre-amorphous by using the method, and then ions are implanted into the entire area.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図(83〜(+11は半導体装置の製造方法を工程を追
って示す断面側面図である。図において、(1)〜f3
1.1511.1E、 @は第2図の従来例に示したも
のと同等であるので説明を省略する。圓、弼はエネルギ
ーの異なるFIB (ただし、イオン種は基板結晶と同
種のものを使用する。通常Siである)。@亀(支)は
上記のエネルギーの異なるFIBによってアモルファス
化されたプリアモルファス領域である。
An embodiment of the present invention will be described below with reference to the drawings. 1st
Figures (83-(+11) are cross-sectional side views showing the manufacturing method of a semiconductor device step by step. In the figure, (1)-(+11)
1.1511.1E and @ are the same as those shown in the conventional example of FIG. 2, so their explanation will be omitted. Round and double are FIBs with different energies (However, the ion species used are the same as the substrate crystal. Usually Si). @Turtle (branch) is a preamorphous region made amorphous by the FIB with different energy.

次に動作について説明する。まず半導体基板結晶(13
上にトランジスタ分離領域(2)及びトランジスタゲー
ト電極(31を従来方法と同様にして形成した後、第1
図(a)に示すごとく一方のトランジスタ領域に、FI
BrllJを用いてプリアモルファス領域間を設ける。
Next, the operation will be explained. First, the semiconductor substrate crystal (13
After forming a transistor isolation region (2) and a transistor gate electrode (31) on the top in the same manner as in the conventional method, the first
As shown in Figure (a), there is an FI in one transistor area.
A gap between preamorphous regions is provided using BrllJ.

次に、第1図(b)に示すごとく他方のトランジスタ領
域に異なるエネルギーのFIB [でプリアモルファス
領域(資)を設ける。最後に第1図(C)に示すごとく
トランジスタ領域の全面に対しイオン注入団を行うが、
上記によりトランジスタ領域のプリアモルファス化がな
されているのでトランジスタ領域の全面に対し同エネル
ギーのイオン注入口を行っても、異なる注入深さのトラ
ンジスタを得ることができる。
Next, as shown in FIG. 1(b), a pre-amorphous region (material) is provided in the other transistor region with a FIB of different energy. Finally, as shown in FIG. 1(C), ion implantation is performed on the entire surface of the transistor region.
Since the transistor region is pre-amorphized as described above, even if ion implantation with the same energy is performed over the entire surface of the transistor region, transistors with different implantation depths can be obtained.

なお、上記実施例では、半導体基板結晶tl)と同種の
イオン種を用いたFIBVlJ、(社)により、プリア
モルファス領域SU、@を設けてから、通常の全面イオ
ン注入Z]Jを行う場合について説明したが、ダイレク
トに異なるエネルギーのFIBイオン注入を用いてトラ
ンジスタ形成も可能である。
In the above example, the pre-amorphous region SU,@ is provided by FIBVlJ, Inc. using the same type of ion species as the semiconductor substrate crystal tl), and then the normal whole surface ion implantation Z]J is performed. Although described above, it is also possible to directly form a transistor using FIB ion implantation with different energies.

また、上記実施例では異なる2種のトランジスタを形成
したが、3つ以上のトランジスタを形成する場合につい
ても同様の効果を奏する。
Further, although two different types of transistors are formed in the above embodiment, the same effect can be achieved even when three or more transistors are formed.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明により製造プロセス工程を簡略
化できること、また局所的なトランジスタ特性の制御が
可能であり、従来のようにイオン注入条件をウェハ間で
変えて実験を行うことは不要になるなどの効果がある。
As described above, this invention simplifies the manufacturing process and allows local control of transistor characteristics, making it unnecessary to conduct experiments by changing ion implantation conditions between wafers as in the past. There are effects such as

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(e)はこの発明の一実施例による半導
体装置の製造方法を示す断面側面図、第2図は従来の半
導体装置の製造方法を示す断面側面図である。図におい
て(1)は半導体基板結晶、(2)はトランジスタ分離
領域、(3)はトランジスタゲート電極、団はイオン注
入、et+、IX5は不純物注入領域、(2)。 弼はFIBlflll、[はプリアモルファス領域であ
る。 なお、図中、同一符号は同一、又は相当部分を示す。
1A to 1E are cross-sectional side views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional side view showing a conventional method for manufacturing a semiconductor device. In the figure, (1) is a semiconductor substrate crystal, (2) is a transistor isolation region, (3) is a transistor gate electrode, group is an ion implantation region, et+, IX5 is an impurity implantation region, and (2).弼 is FIBlfllll, [ is a preamorphous region. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 半導体装置の製造プロセスにおいて、FIB(収束イオ
ンビーム:Focused Ion Beam)を用い
て、所望の領域をプリアモルファス化し、その後にイオ
ン注入を行うことを特徴とする半導体装置の製造方法。
1. A method for manufacturing a semiconductor device, comprising making a desired region preamorphous using an FIB (Focused Ion Beam), and then performing ion implantation.
JP2171289A 1989-01-30 1989-01-30 Manufacture of semiconductor device Pending JPH02201922A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2171289A JPH02201922A (en) 1989-01-30 1989-01-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2171289A JPH02201922A (en) 1989-01-30 1989-01-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02201922A true JPH02201922A (en) 1990-08-10

Family

ID=12062677

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2171289A Pending JPH02201922A (en) 1989-01-30 1989-01-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02201922A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7732291B2 (en) 2006-04-28 2010-06-08 Globalfoundries Inc. Semiconductor device having stressed etch stop layers of different intrinsic stress in combination with PN junctions of different design in different device regions
US7811876B2 (en) 2008-02-29 2010-10-12 Globalfoundries Inc. Reduction of memory instability by local adaptation of re-crystallization conditions in a cache area of a semiconductor device
US8034726B2 (en) 2007-12-31 2011-10-11 Advanced Micro Devices, Inc. Interlayer dielectric material in a semiconductor device comprising a doublet structure of stressed materials

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7732291B2 (en) 2006-04-28 2010-06-08 Globalfoundries Inc. Semiconductor device having stressed etch stop layers of different intrinsic stress in combination with PN junctions of different design in different device regions
DE102006019936B4 (en) * 2006-04-28 2015-01-29 Globalfoundries Inc. Semiconductor device with differently strained etch stop layers in conjunction with PN junctions of different design in different device areas and method for producing the semiconductor device
US8034726B2 (en) 2007-12-31 2011-10-11 Advanced Micro Devices, Inc. Interlayer dielectric material in a semiconductor device comprising a doublet structure of stressed materials
US7811876B2 (en) 2008-02-29 2010-10-12 Globalfoundries Inc. Reduction of memory instability by local adaptation of re-crystallization conditions in a cache area of a semiconductor device

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